LTC4100 datasheet(5/24 Pages) LINER

5 / 24 page

LTC4100

sn4100 4100is

The q denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VDD = 3.3V, VBAT = 12V unless otherwise noted. (Note 4)

ELECTRICAL CHARACTERISTICS

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: See Test Circuit.

Note 3: Does not include tolerance of current sense resistor.

Note 4: The LTC4100E is guaranteed to meet performance specifications

from 0

°C to 70°C. Specifications over the –40°C to 85°C operating

temperature range are assured by design, characterization and correlation

with statistical process controls.

Note 5: Current accuracy dependent upon circuit compensation and sense

resistor.

Note 6: CTH is defined as the sum of capacitance on THA, THB and

SafetySignal.

Note 7: The corresponding overrange bit will be set when a HEX value

greater than or equal to this value is used.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Charging Voltage Limit

RVLIM = 0

8.730

8.800

8.870

Charging Voltage = 0x2260 (Note 7)

RVLIM = 10k ±1%

12.999

13.104

13.209

Charging Voltage = 0x3330 (Note 7)

RVLIM = 33k ±1%

17.269

17.408

17.547

Charging Voltage = 0x4400 (Note 7)

RVLIM = 100k ±1%

21.538

21.712

21.886

Charging Voltage = 0x5400 DCIN

≥ 22V (Note 7)

RVLIM = 0pen (or Short to VDD)

27.781

28.006

28.231

Charging Voltage = 0x6D60 DCIN

≥ 29V (Note 7)

Logic Levels

VIL

SCL/SDA Input Low Voltage

0.8

VIH

SCL/SDA Input High Voltage

2.1

VOL

SDA Output Low Voltage

IPULL-UP = 350µA

0.4

IIL

SCL/SDA Input Current

VSDA, VSCL = VIL

–1

µA

IIH

SCL/SDA Input Current

VSDA, VSCL = VIH

–1

µA

VOL

SMBALERT Output Low Voltage

IPULL-UP = 500µA

0.5

SMBALERT Output Pull-Up Current

VSMBALERT = VOL

–17.5

–10

–3.5

µA

VOL

CHGEN Output Low Voltage

IOL = 100µA

0.4

CHGEN Output Pull-Up Current

VCHGEN = VOL

–17.5

–10

–3.5

µA

VIL

CHGEN Input Low Voltage

0.9

VIH

CHGEN Input High Voltage

VDD = 3V

2.5

VDD = 5.5V

3.9

Power-On Reset Duration

VDD Ramp from 0V to >3V in <5µs

100

µs

SMBus Timing (Refer to System Management Bus Specification, Revision 1.1, Section 2.1 for Timing Diagrams)

tHIGH

SCL Serial Clock High Period

IPULL-UP = 350µA, CLOAD = 250pF, RPU = 9.31k

µs

tLOW

SCL Serial Clock Low Period

IPULL-UP = 350µA, CLOAD = 250pF, RPU = 9.31k

4.7

15000

µs

SDA/SCL Rise Time

CLOAD = 250pF, RPU = 9.31k

1000

SDA/SCL Fall Time

CLOAD = 250pF, RPU = 9.31k

300

tSU:STA

Start Condition Setup Time

4.7

µs

tHD:STA

StartCondition Hold Time

µs

tHD:DAT

SDA to SCL Falling-Edge Hold Time,

300

Slave Clocking in Data

tTIMEOUT

Time Between Receiving Valid

140

175

210

sec

ChargingCurrent() and

ChargingVoltage() Commands

LTC4100 Datasheet(PDF) 5 Page - Linear Technology

LTC4100 Datasheet(HTML) 5 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL