Nexperia

74HC3G07; 74HCT3G07

Triple buffer with open-drain outputs

VM

VM

tW

tW

10 %

90 %

0 V

VI

VI

negative

pulse

positive

pulse

0 V

VM

VM

90 %

10 %

tf

tr

tr

tf

001aad983

DUT

VCC

VCC

VI

VO

RT

RL

S1

CL

open

G

Test data is given in Table 10.

Definitions for test circuit:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance.

RL = Load resistance.

S1 = Test selection switch.

Fig. 6. Test circuit for measuring switching times

Table 10. Test data

Input

Load

S1 position

Type

VI

tr, tf

CL

RL

tPZL, tPLZ

74HC3G07

GND to VCC

≤ 6 ns

50 pF

1 kΩ

VCC

74HCT3G07

GND to 3 V

≤ 6 ns

50 pF

1 kΩ

VCC

74HC_HCT3G07

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© Nexperia B.V. 2019. All rights reserved

Product data sheet

Rev. 5 — 24 January 2019

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