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CS5535 Datasheet(PDF) 518 Page - National Semiconductor (TI) |
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CS5535 Datasheet(HTML) 518 Page - National Semiconductor (TI) |
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518 / 555 page  www.national.com 518 Revision 0.8 GLCP Register Descriptions (Continued) 5.20.2 GLCP Specific MSRs These registers are used for power management, and facilitate some clock and reset functions. The “CLK” associated reg- isters (i.e., CLKACTIVE, CLKOFF, CLKDISABLE, CLK4ACK and PMCLKDISABLE) have the same layout where each bit is associated with a clock domain. The layout and recommended operating values for the “CLK” associated registers is shown in Table 5-73. For additional discussion on clock management considerations, see Section 3.5 "Clock Considerations" on page 57. Table 5-73. Clock Mapping / Operational Settings MSR Bit Name/Description GLCP Register CLK ACTIVE CLK OFF CLK DISABLE CLK 4ACK PM CLK DISABLE CLK[63:34] RSVD. Reserved for future use by National. RO 0000 CLK33 GLCP_PCI. GLCP PCI Clock. RO 0000 CLK32 GLCP_DBG. GLCP DBG Logic Clock. RO 0000 CLK31 GLCP_GLIU. GLCP GeodeLink Clock. RO 0000 CLK30 DIVIL_MFGPT_32K_STD. MFGPT 32 kHz Standby Clock entering DIVIL. RO 0000 CLK29 DIVIL_MFGPT_14M. MFGPT 14 MHz Clock entering DIVIL. RO 0000 CLK28 DIVIL_MFGPT_32K. MFGPT 32 kHz Clock entering DIVIL. RO 0000 CLk27 DIVIL_GPIO_STD. GPIO Standby Clock entering DIVIL. RO 0000 CLK26 DIVIL_GPIO. GPIO Clock entering DIVIL. RO 0000 CLK25 DIVIL_PMC_STD. PMC Standby Clock. RO 0000 CLK24 DIVIL_PMC. PMC Working Logic Clock. RO 0000 CLK23 DIVIL_UART2. UART2 Clock entering DIVIL. RO 0010 CLK22 DIVIL_UART1. UART1 Clock entering DIVIL. RO 0010 CLK21 DIVIL_PIT. PIT Clock entering DIVIL. RO 0000 CLK20 DIVIL_SMB. SMB Clock entering DIVIL. RO 0010 CLK19 DIVIL_DMA. DMA Clock entering DIVIL. RO 0010 CLK18 DIVIL_LPC. LPC Clock entering DIVIL. RO 0010 CLK17 DIVIL_LB. LBus Clock entering DIVIL. RO 0010 CLK16 DIVIL_GLIU. GeodeLink (GLIU) Clock entering DIVIL. RO 0010 CLK15 ACC_BIT. AC97 Clock entering ACC. RO 0000 CLK14 ACC_LB. 33 MHz Clock entering ACC. RO 0010 CLK13 ACC_GLIU. GeodeLink (GLIU) Clock entering ACC. RO 0010 CLK12 ATAC_LB. 66 MHz Clock entering ATAC. RO 0010 CLK11 ATAC_GLIU. GeodeLink (GLIU) Clock entering ATAC. RO 0010 CLK10 USB2_48M. 48 MHz Clock entering USB (ports 3 & 4). RO 0010 CLK9 USB1_48M. 48 MHz Clock entering USB (ports 1 & 2). RO 0010 CLK8 USB2_LB. 33 MHz Clock entering USB (ports 3 & 4). RO 0010 CLK7 USB1_LB. 33 MHz Clock entering USB (ports 1 & 2). RO 0010 CLK6 USB2_GLIU. GeodeLink (GLIU) Clock entering USB (ports 3 & 4). RO 0010 CLK5 USB1_GLIU. GeodeLink (GLIU) Clock entering USB (ports 1 & 2). RO 0010 CLK4 GLPCI_PCIF. Fast PCI Clock for chip I/O interface. RO 0000 CLK3 GLPCI_PCI. Normal PCI Clock for GLPCI_SB logic. RO 0010 CLK2 GLPCI_GLIU. GeodeLink (GLIU) Clock entering GLPCI_SB. RO 0010 CLK1 GL0_1. GeodeLink (GLIU) operational logic clock. RO 0010 CLK0 GL0_0. GeodeLink (GLIU) clock to timer logic. RO 0000 |
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