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CS5535 Datasheet(PDF) 519 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # CS5535
Description  Geode??CS5535 I/O Companion Multi-Function South Bridge
PDF  555 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

CS5535 Datasheet(HTML) 519 Page - National Semiconductor (TI)

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519
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GLCP Register Descriptions (Continued)
5.20.2.1
GLCP Clock Disable Delay Value (GLCP_CLK_DIS_DELAY)
This register has bits that, when set, disable clocks.
5.20.2.2
GLCP Clock Mask for Sleep Request (GLCP_PMCLKDISABLE)
MSR Address
51700008h
Type
R/W
Reset Value
00000000_00000000h
GLCP_CLK_DIS_DELAY Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
98
7654321
0
RSVD
CLK_DELAY
GLCP_CLK_DIS_DELAY Bit Descriptions
Bit
Name
Description
63:24
RSVD
Reserved.Reads as 0
23:0
CLK_DELAY
Clock Disable Delay. If enabled in GLCP_GLB_PM (MSR 5170000Bh[1] = 1), this field
indicates the period to wait from the assertion of SUSPA# before gating-off clocks speci-
fied in GLCP_PMCLKDISABLE (MSR 51700009h). If this delay is enabled, it overrides or
disables the function of GLCP_CLK4ACK (MSR 51700013h). If GLCP_GLB_PM enable
bit is not set (MSR 5170000Bh[1] = 0), but this register (GLCP_CLK_DIS_DELAY) is non-
zero, then this register behaves as a timeout for the CLK4ACK behavior. Note that this
number is in terms of PCI clock cycles, divided by 16.
MSR Address
51700009h
Type
R/W
Reset Value
00000000_00000000h
GLCP_PMCLKDISABLE Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
98
7654321
0
GLCP_PMCLKDISABLE Bit Descriptions
Bit
Name
Description
63:34
RSVD
Reserved
33:0
CLK_DIS
Clock Disable. The bits in this field correspond to the Clock Off (CLK_OFF) bits in
GLCP_CLKOFF (MSR 51700010h). If a bit in this field is set, then the corresponding
CLK_OFF bit will be set when the power management circuitry disables clocks when
entering Sleep. For bit-to-clock correspondences and recommended operational settings
see Table 5-73 on page 518.



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