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CS5535 Datasheet(PDF) 523 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # CS5535
Description  Geode??CS5535 I/O Companion Multi-Function South Bridge
PDF  555 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

CS5535 Datasheet(HTML) 523 Page - National Semiconductor (TI)

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GLCP Register Descriptions (Continued)
5.20.2.10 GLCP Clock Active Mask for Suspend Acknowledge (GLCP_CLK4ACK)
This register has bits that correspond to the Clock Active (CLK_ACT) bits in GLCP_CLKACTIVE (MSR 51700011h). If the
bit in GLCP_CLK4ACK is set, then the SUSPA# signal will not go low unless all the marked clocks are inactive.
5.20.2.11 GLCP System Reset Control (GLCP_SYS_RST)
Writing 1 to the CHIP_RESET bit creates a chip-wide reset and in turn, resets this register. Writing this register with the
CHIP_RESET bit set will never send a write-response over the GLIU Interface (this allows halting bus traffic before the
reset occurs).
MSR Address
51700013h
Type
R/W
Reset Value
00000000_00000000h
GLCP_CLK4ACK Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
98
7654321
0
GLCP_CLK4ACK Bit Descriptions
Bit
Name
Description
63:34
RSVD
Reserved
33:0
CLKACT_EN_SLP
Clock Active Enable for Sleep. A 1 in any bit position indicates the corresponding
clock is to be monitored during a power management Sleep operation. When all the
clocks with associated 1s become inactive, the GLCP sends a Suspend Acknowledge
(SUSPA#) to the power management logic to begin the transition to the Sleep state. Use
of this register during Sleep sequences requires the CLK_DLY_EN bit (MSR
5170000Bh[1]) to be 0. For bit-to-clock correspondences and recommended operational
settings see Table 5-73 on page 518.
MSR Address
51700014h
Type
R/W
Reset Value
00000000_00000000h
GLCP_SYS_RST Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
98
7654321
0
RSVD
RSVD
GLCP_SYS_RST Bit Descriptions
Bit
Name
Description
63:24
RSVD
Reserved. Reads as 0.
23:1
RSVD
Reserved. These bits can be read/written but should not be used; write to 0.



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