CS5535 datasheet(148/555 Pages) NSC

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GPIO Subsystem Functional Description (Continued)

4.15.2 Register Strategy

The register set for the GPIO subsystem has been

arranged in such a way as to eliminate the need for read-

modify-write operations. Individual GPIO control bits may

be directly and immediately altered without requiring

knowledge of any other GPIO states or bit settings. Previ-

ous systems required the current settings for all GPIOs to

be read, selected pins changed, and the result written

back. If this read-modify-write operation was interrupted by

another process that also used the GPIOs, then erroneous

operation could result.

To avoid the read-modify-write operation, two data bits are

used to control each GPIO feature bit, wherein a feature is

enabled or disabled. One register bit is used to establish a

logic 1, while a second register bit is used to establish a

logic 0. A 1 in a register bit changes the feature bit’s value,

while a 0 does nothing. Since there are two register bits for

each feature bit, for each GPIO, there are four combina-

tions of register bits possible. The two control bits operate

in an exclusive-OR pattern, as illustrated in Table 4-30.

An example 16-bit register controlling a feature bit for eight

GPIOs is illustrated in Table 4-31. Note that the real regis-

ters are 32 bits; 16 bits are used here as an illustrative

example.

Assume that the register in Table 4-31 allows setting and

clearing of an unspecified “feature bit” for GPIO[7:0].

Assume that the 16-bit value given in the example has just

been written into the register. In this example, all four possi-

ble bit combinations fromTable 4-30 are examined.

GPIO5 has a 0 in the logic 0 bit position (register bit 13),

and a 1 in the logic 1 bit position (register bit 5), so the

GPIO5 feature bit would become a 1.

GPIO4 has a 1 in the logic 0 bit position (register bit 13),

and a 0 in the logic 1 bit position (register bit 5), so the

GPIO4 feature bit would become a 0.

GPIO7 has a 1 in both bit positions 15 and 7. Writing a 1 to

both the logic 1 and logic 0 bit positions causes no change

to the GPIO7 feature bit.

GPIO6 has a 0 in both bit positions 14 and 6. Writing a 0 to

both the logic 1 and logic 0 bit positions causes no change

to the GPIO6 control bit. GPIO[3:0], also have 0s in both bit

positions, so they experience no change.

Reads produce a normal and an inverted value. For exam-

ple, assume the Output Enable is set only for GPIO4 in the

above register. A read would return the value EF10h.

Actual GPIO registers associated with feature bit settings

are 32 bits wide and each handle 16 GPIOs. They are

organized into low and high banks. The low bank deals with

GPIO[15:0], while the high bank deals with GPIO[28:24]

and GPIO[22:16].

In addition to these “bit registers”, there are value registers

for the Input Conditioning Functions.

4.15.3 Lock Bits

Many GPIO registers are protected against accidental

changes by Lock Enable registers that prevent further

changes. Once a LOCK bit is set, the associated register

can not be changed until the corresponding LOCK bit is

cleared. There are two Lock Bit registers, one for the high

bank (GPIOH_LOCK_EN, GPIO I/O Offset 8Ch) and one

for the low bank (GPIOH_LOCK_EN, GPIO I/O Offset

3Ch). All GPIO registers are protected by LOCK bits except

the

High

and

Low

Bank

Read

Back

registers,

(GPIO[x]_READ_BACK), High and Low Bank Positive

Edge Status registers (GPIO[x]POSEDGE_STS), the High

Low

Bank

Negative

Edge

Status

registers

(GPIO[x]NEGEDGE_STS), and of course the Lock Enable

registers themselves.

Table 4-30. Effect on Feature Bit

Logic 0

Bit

Position

Logic 1

Bit

Position

Effect on Feature Bit

No change

Feature bit is cleared to 0

Feature bit is set to 1

No change

Table 4-31. 16-Bit GPIO Control Register Example

Bit No.

“1” Sets Control Bit to 0

“1” Sets Control Bit to 1

765

432

Value

010

000

101

000

GPIO #

543

210

765

432

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