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GPIO Subsystem Functional Description (Continued)

4.15.5 Input Conditioning Functions

GPIOs in the CS5535 may have their inputs conditioned by

configurable circuitry as illustrated in Figure 4-49 on page

149. Any GPIO may be connected to one of eight Input

Conditioning functions, each consisting of a Digital Filter

and an Event Counter (known as an Event/Filter pair).

Each GPIO is followed by an edge detection function that

may be set for either positive or negative going edges. As

shown in Figure 4-49, the edge detection function may be

used to monitor the output of the Event/Filter pair that has

been associated with that particular GPIO, or it may be

used independently of the Event /Filter pair.

These functions are enabled as follows:

• IN_FLTR_EN. Enables the input filter function of the

associated GPIO.

• EVNTCNT_EN. Enables the event counter function of

the associated GPIO.

• IN_POSEDGE_EN and IN_NEGEDGE_EN. Enables

the edge detection function and mode.

The final input value may be read back by a software

accessible register (GPIO[x]_READ_BACK). It may also be

used as an Interrupt or a Power Management Event.

There are a total of eight Digital Filter/Event Counter pairs

that are shared by 28 GPIOs. There is a selection function

to associate a given Filter/Counter pair with a given GPIO.

All GPIOs incorporate edge detection.

4.15.5.1 Input Filter Conditioning Function

The digital filter is one-half of a Filter/Event conditioning cir-

cuit. (The other half is the Event Counter.) The filter is used

to produce a stable output from an unstable input. Mechan-

ical switch de-bounce is a typical use.

To use one of the eight digital filters, it must first be

assigned to one of the GPIO inputs using one of the

GPIO_FE[x]_SEL registers (GPIO I/O Offsets F0h-F7h);

where “x” is the number of the Filter/Event pair, 0 to 7.

Then the filter function must be enabled through either the

GPIOL_IN_FLTR_EN (GPIO I/O Offset 28h) or the

GPIOH_IN_FLTR_EN (GPIO I/O Offset A8h) registers,

depending on whether the selected GPIO is in the high

[28:16] or low [15:0] bank. Finally, a GPIO_FLTR[x]_AMNT

(GPIO I/O Offsets 50h, 58h, 60h, 68h, 70h, 78h, D0h, and

D8h) must be determined and then programmed to estab-

lish the filter’s stability period.

The associated GPIO input must ultimately remain stable

for a

FLTR_AMNT number of 32 kHz clock edges in order

for the output to change. A

FLTR_AMNT of 0 effectively

disables the filtering function, because the counter will not

roll over from 0 to all 1s. The maximum

FLTR_AMNT is

FFFFh.

The digital filter is based upon a 16-bit programmable

down-counter. An initial count is loaded into the counter via

the GPIO_FLTR[x]_AMNT register. When the associated

GPIO input changes, the counter begins counting down

from FLTR_AMNT towards 0. If the associated GPIO input

remains stable for the length of the count-down period,

then the counter reaches 0 and produces an output pulse

to whatever the GPIO is internally connected to. If the

associated GPIO input changes during the count-down

period, then the counter reloads the initial count from the

GPIO_FLTR[x]_AMNT register and begins counting down

towards 0 again.

Direct access to the counter’s state is provided by the R/W

to determine the current value of the counter. The

GPIO_FLTR[x]_CNT register may also be written to at any

time, thereby jamming the counter state forward or back-

ward from the current count.

Reads and writes of the GPIO_FLTR[x]_CNT register are

internally synchronized to avoid false read values and cor-

rupted writes, that is, reads and writes may occur to a filter

circuit without concern of the phasing or timing of the 32

kHz clock edges. When GPIO[x]_IN_FLTR_EN is low the

filter circuit is not clocked.

The filter circuit is used to produce a stable output from an

unstable input. Mechanical switch de-bounce is a typical

use. The default value for all flip-flops, the Down Counter,

and the Filter Amount Register is zero. Software estab-

lishes the filter amount. As long as the preliminary input on

the left matches the filtered input on the right, the circuit is

stable and the counter continuously loads the filter amount

value. When the preliminary input changes, the counter

begins to count. If the input remains steady, then the

counter reaches zero and enables loading the value flip-

flop. This brings the circuit back to the stable point. If the

input does not remain steady, then the counter reloads.

The preliminary input on the left must remain steady the

“filter amount” number of clock edges for the final input on

the right to change. A filter amount of zero effectively dis-

ables the filtering function because the Down Counter will

not roll over backwards to all ones. The maximum filter

amount is FFFFh

4.15.5.2 Input Event Counter Conditioning Function

The event counter is one half of a filter/event conditioning

circuit, and is in series with its associated filter. (The other

half is the digital filter.) It counts events and can produce an

output when a predefined count is reached. The event

counter may be down-counted by writing to a particular

address. It may be used as a rate counter that may be peri-

odically read, and that produces no output at all.

To use one of the eight event counters, it must first be

assigned to one of the GPIO inputs using one of the

GPIO_FE[x]_SEL registers (where X is the number of the

Filter/Event pair, 0 to 7). Then the associated digital filter

must be enabled, through either the GPIOL_IN_FLTR_EN

or GPIOH_IN_FLTR_EN registers, depending on whether

the selected GPIO is in the high [28:16] or low [15:0] bank.

If digital filtering is not required, program the associated

GPIO_FLTR[x]_AMNT registers to 0000h. Finally, the

desired

“compare

value”

(GPIO_EVNTCNT[x]

_COMPARE) must be determined and then programmed to

establish the number of events that will produce an output

when that count has been reached.

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