CS5535 datasheet(154/555 Pages) NSC

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MFGPT Functional Description (Continued)

4.16.1 Prescaler

The 15-bit prescaler is a binary down counter, dividing

down the incoming clock, and provides 15 outputs for the

MFGPTs. The frequency of these outputs ranges from 2-1

to 2-15 of the input frequency and each pulse is one incom-

ing clock high, so these outputs function as increment

enables for the MFGPTs. The prescaler resets to 000016

and starts decrementing after reset. The prescaler output

vector, psclr_out[14:0], is based on prescaler counter

psclr_cnt[14:0], where psclr_out[i] = &(~psclr_cnt[i:0]) (i.e.,

prescaler output bit i is asserted if the prescaler counter

from bit i down to bit 0 are all low). When the prescaler

reaches 000016, all prescaler outputs are asserted at that

time.

The external clock for the prescaler is activated if there is

one or more MFGPTs activated using it as its clock source;

it is also activated for MFGPT I/O register writes and syn-

chronous counter reads (only for 14.318 MHz) when the

MFGPT being written has already selected the 14.318 MHz

clock as its clock source. Whenever the external clock is

activated,

the

prescaler

counts.

Therefore,

multiple

MFGPTs and register access can affect the prescaler

counting. From the point of view of the MFGPT, once the

MFGPT is disabled and then re-enabled, it cannot be

determined exactly when the prescaler carry-out occurs as

it does not know how long the prescaler has been stopped,

if at all.

4.16.2 I/O Registers Block

The I/O register write data is first stored in I/O register sub-

modules before being transferred over to the MFGPTs.

There are two types of I/O register sub-modules, one for

the Working power domain and one for the Standby power

domain. The main difference is that for the Working power

domain, except for the counter register, the register values

here and the register values in the timer are the same. For

the Standby power domain, the register values in the I/O

write, as this logic could have been powered down in

Standby mode and the register data is therefore invalid.

For the Standby power domain, the read always comes

from the timer directly.

4.16.2.1 MFGPT Register Set

There are four software accessible I/O registers per

MFGPT: Up Counter, Comparator 1 Value, Comparator 2

Value, and Setup registers. (See Section 5.17 "Multi-Func-

tion General Purpose Timer Register Descriptions" on

page 466 for register details.) Writes to these registers are

first stored here and then transferred to a separate copy of

the register in the timer. For MFGPT0 to MFGPT5, read of

these registers, except for the counter, comes from the reg-

isters here, while read of the counter register comes from

the timer. For MFGPT6 and MFGPT7, reads of these regis-

ters comes from the copy inside the timer. (TW Note:

Restate reason or be more precise in reference.)

4.16.2.2 Setup Register

The Setup Register contains the following control fields that

control the MFGPT operation:

• Counter Enable. Enables the Up Counter to count (it

does not enable/disable other MFGPT functions).

• Clock Select. Instructs the clock switch logic to use the

32 kHz clock as the MFGPT clock if low or the 14.318

MHz clock if high, once this register has been written

(only for MFGPT0 to MFGPT5).

• Scale Factor. Selects the prescaler divide scale factor

for Up Counter to increment.

•Stop Enable. Enables the Up Counter to stop counting

during a system power management Sleep mode (for

MFGPT0 to MFGPT5) or Standby mode (for MFGPT6

and MFGPT7).

• External Enable. Enables the Up Counter to be cleared

and restarted rather than performing the next increment

each time there is a low to high transition detected on

the GPIO input associated with the timer. An asynchro-

nous edge-detector catches the transition; the signal is

then synchronized and sent to clear the counter

synchronously. Therefore, the clear does not occur

immediately on the transition.

• Reverse Enable. Flips the order of the Up Counter

outputs going to the Compare 1 circuit so that bit 0

becomes bit 15, bit 1 becomes bit 14, etc. This allows

the timer logic to generate a PDM signal instead of a

PWM signal. To properly generate a PDM signal, the

Compare 2 Value should be set to FFFF16 to allow the

Compare 1 Value to establish the density.

• Compare 1 Mode. Controls the Compare 1 output.

There are four cases:

00: Disabled. Output is low.

01: Compare on Equal. The compare output goes high

when the Up Counter value, after going through Bit

Reverse logic, is the same value as the Compare 1

Value.

10: Compare on GE. The compare output goes high

when the Up Counter value, after going through Bit

Reverse logic, is greater than or equal to the Compare

1 Value.

11: Event. Same as “Compare on GE”, but an event is

also created. This event can be read and cleared via

the MFGPT Setup Register and is used to generate

interrupt and reset.

• Compare 2 Mode. Same as Compare 1 Mode, except

this controls the Compare 2 output. The Up Counter is

directly compared against the Compare 2 Value (i.e.,

without going through Bit Reverse logic).

All of the above fields, except Count Enable, are write-once

only.

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