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CS5535 Datasheet(PDF) 153 Page - National Semiconductor (TI) |
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CS5535 Datasheet(HTML) 153 Page - National Semiconductor (TI) |
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153 / 555 page ![]() Revision 0.8 153 www.national.com 4.16 MULTI-FUNCTION GENERAL PURPOSE TIMER The Multi-Function General Purpose Timer module con- tains eight multi-function general purpose timers (MFGPTs). Six of the eight MFGPTs are in the Working power domain running off a 32 kHz clock or a 14.318 MHz clock, while the other two are in the Standby power domain running off a 32 kHz clock. The Working power domain contains the following blocks: • Six MFGPTs each split into three blocks, one containing I/O registers, one containing the clock switch, and one containing the timer logic. • 15-bit prescaler to divide down the 14.318 MHz clock and generate 15 carry-out signals. • 15-bit prescaler to divide down the 32 kHz clock and generate 15 carry-out signals. • Logic to implement Local Bus Interface, Control Logic, MSR Registers, and NMI, IRQ, and Reset Output Events. • Two blocks containing I/O registers to write into the two MFGPTs in the Standby power domain. The Standby power domain contains the following blocks: • Two MFGPTs. • 15-bit prescaler to divide down the 32 kHz clock and generate 15 carry-out signals. • Interface for signals going between Standby and Working power domains. Figure 4-50 shows the top level block diagram of the Multi- Function General Purpose Timer module. Features Each MFGPT operates independently and can have the following features: • 32 kHz or 14.318 MHz clock selectable by software (MFGPT0 to MFGPT5 only; MFGPT6 and MFGPT7 use 32 kHz clock). • Programmable input clock prescaler divisor to divide input clock by 2i, where i = 0 to 15. • Watchdog timer (trigger GPIO output, interrupt, or reset). • Pulse Width Modulation (PWM). • Pulse Density Modulation (PDM). • Blink (low frequency pulse for LED). • General Purpose Timer. • Generate GPIO outputs. • Provide outputs for generating reset (limited to MFGPT0 to MFGPT5), IRQs, NMI, and ASMI (indirectly through PIC). Figure 4-50. MFGPT System Top Level Block Diagram Working Domain Control and MSR Registers MFGPT0 MFGPT6 Power Domain Crossing I/F Standby Domain 14.318 MHz 32 kHz Prescaler Prescaler 32kHz Prescaler I/O Reg Clock Switch Timer MFGPT1 I/O Reg Clock Switch Timer MFGPT2 I/O Reg Clock Switch Timer MFGPT3 I/O Reg Clock Switch Timer MFGPT4 I/O Reg Clock Switch Timer MFGPT5 I/O Reg Clock Switch Timer I/O Reg I/F MFGPT7 I/O Reg I/F MFGPT6 Timer MFGPT7 Timer |
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