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CS5535 Datasheet(PDF) 158 Page - National Semiconductor (TI) |
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CS5535 Datasheet(HTML) 158 Page - National Semiconductor (TI) |
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158 / 555 page  www.national.com 158 Revision 0.8 MFGPT Functional Description (Continued) 4.16.5 Working Power Domain Logic The Working power domain logic consists of the Local Bus Interface, Control Logic, MSRs, and NMI, IRQ, and Reset Output Events. When Event mode is enabled, the NMI, IRQ, and Reset Output Events logic gathers the event outputs of all eight MFGPTs and then generates the interrupt and resets out- puts based on MSR settings. The interrupt outputs go to the PIC that can then trigger an IRQ or ASMI. Note that MFGPT6 and MFGPT7 cannot trigger reset. These outputs are controlled by MSR bits, and the NMI output can be fur- ther controlled by the MSB of I/O Address 070h. 4.16.6 Power Domain Crossing Interface Logic The asynchronous internal Standby State signal will dis- able/enable the Working power domain interface immedi- ately. Therefore, any bus operation active at that time will have an indeterminate result. Table 4-33. MFGPT Pulse Density Modulation Example Up Counter Output Bit Reverse Output Pulse Train Output for Given Compare 1 Value (Note 1) 124 56 000 000 0 0 0 0 0 001 100 1 1 1 0 0 010 010 1 1 0 0 0 011 110 1 1 1 1 1 100 001 1 0 0 0 0 101 101 1 1 1 1 0 110 011 1 1 0 0 0 111 111 1 1 1 1 1 Note 1. Compare 2 Value must be set to all 1s for pulse density modulation. |
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