AD7143 datasheet(39/56 Pages) AD

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AD7143

Rev. 0 | Page 39 of 56

Table 22. STAGE_HIGH_INT_EN Register

Address

Data Bit

Default

Type

Name

Description

[0]

STAGE0_HIGH_INT_EN

STAGE0 high interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 high threshold is exceeded

[1]

STAGE1_HIGH_INT_EN

STAGE1 high interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 high threshold is exceeded

[2]

STAGE2_HIGH_INT_EN

STAGE2 high interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 high threshold is exceeded

[3]

STAGE3_HIGH_INT_EN

STAGE3 high interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 high threshold is exceeded

[4]

STAGE4_HIGH_INT_EN

STAGE4 high interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 high threshold is exceeded

[5]

STAGE5_HIGH_INT_EN

STAGE5 high interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 high threshold is exceeded

[6]

STAGE6_HIGH_INT_EN

STAGE6 high interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 high threshold is exceeded

[7]

STAGE7_HIGH_INT_EN

STAGE7 high interrupt enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 high threshold is exceeded

0x006

[15:8]

R/W

Unused

Set unused register bits = 0

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