UG Series

5–2

Rev. B

Product Outline

Part Number

Full programmables Pads

Equivalent FPGA Gates

Maximum Drive

UG01

30

3300

N/A

UG04

48

7500

310

UG09

72

15800

790

UG14

88

24300

1210

UG20

104

34800

1740

UG33

130

46000

2880

UG42

146

58600

3660

UG52

162

63700

4550

UG70

188

85800

6130

UG90

212

108500

7750

UG120

244

145100

10360

UG140

264

156800

12250

Architecture

The basic element of the UG family is called a cell. One

cell can typically implement between two to three FPGA

gates. Cells are located contiguously through out the

core of the device, with routing resources provided in

two or three metal layers above the cells. Some cell

blockage does occur due to routing, and utilization will

be significantly greater with three metal routing than

two.

The sizes listed in the Product Outline are

estimated usable amounts using three metal layers. I/O

cells are provided at each pad, and may be configured as

any FPGA or PLD pinout. Special function cells and

pins are located in the corners which typically are

unused.

In order to improve noise immunity within the device,

internal cells and the I/O cells.

I/O Options

Inputs

Each input can be programmed as TTL, CMOS, or

Schmitt Trigger, with or without a pull up or pull down

resistor.

Fast Output Buffer

Fast output buffers are able to source or sink 3 to 12 mA

according to the chosen option. 24mA achievable, using

2 pads.

Slew Rate Controlled Output Buffer

In this mode, the p- and n-output transistor commands

are delayed, so that they are never set “ON”

simultaneously, resulting in a low switching current and

low noise. These buffer are dedicated to very high load

drive.

3.3V Compatibility

The UG series of ULCs is fully capable of supporting

high-performance operation at 3.3V or 5.0V.

The

performance specifications of any given ULC design

however, must be explicitly specified as 3.3V, 5.0V or

both.

Power Supply and Noise Protection

In order to improve the noise immunity of the UG series,

several mechanisms have been implemented inside the

UG devices. Two kinds of protection have been added:

one to limit the I/O buffer switching noise and the other

to protect the I/O buffers against the switching noise

coming from the core.

I/O buffers switching protection

Three features are implemented to limit the noise

generated by the switching current: The power supplies

of the input and output buffer are separated. The rise and

fall times of the output buffers can be controlled. The

number of buffers that are connected on the same power

supply line is limited.