UG Series

5–4

Rev. B

Internal Timing Characteristics

These timing parameters for selected macro cells are

provided for information only. Only pin-to-pin timing

characteristics are guaranteed for ULCs, and the actual

specification is determined by the original FPGA or

PLD data sheet plus any specific parameters that are

agreed

to

separately

by

Atmel

Wireless

&

Microcontrollers.

Macro Type

Parameter

Symbol

Min

Units

2-Input NAND

NAND2

0.39

0.56

4-Input NAND

NAND4

0.68

0.88

Inverter

INV

Propagation Time

0.41

0.68

ns

0.74

0.99

Inverting Tri-State Buffer

TRISTAN

Enable Time

0.69

0.97

Setup Time

0.60

Hold Time

0.00

Pulse Width

Resetable Latch

LATCHR

Propagation Time

0.97

1.25

Enable Time

1.22

1.49

Reset Time

0.87

1.10

Setup Time

0.40

Hold Time

0.00

D Flip-Flop with Reset

FDFFR

Pulse Width

0.60

Clock Delay Time

0.95

1.22

Reset Time

0.81

0.94

TTL Compatible Input

0.80

0.95

TTL Compatible Input

Buffer

BUFINTTL

0.68

0.74

ns

TTL Compatible I/O Buffer

0.80

0.95

TTL Compatible I/O Buffer

Input Mode

BIOT12

0.68

0.74

Propagation Time

2.97

8.18

Output Buffer

BOUT6

1.96

4.23

2.49

6.42

1.74

3.47

TTL Compatible I/O Buffer

BIOT12

3.27

7.17

Enable Time

1.60

3.30

2.49

6.42

Propagation Time

1.74

3.47

Tri-State Output Buffer

B3STA12

3.27

7.17

Enable Time

1.60

3.30

Notes

20 pF, BIOT12 and B3STA12 are 30 pF.

b. Fan-outs are six internal loads for NAND2, seven loads for NAND4, nine loads for all other internal macros and eight for the input buffer.