MP1922 – 100V, 3A, SINGLE-CHANNEL, HALF-BRIDGE PRE-DRIVER IC

MP1922 Rev. 1.0

www.MonolithicPower.com

13

9/10/2021

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

© 2021 MPS. All Rights Reserved

The state of the nFAULT pin is sampled at

start-up. If nFAULT is low, then the desaturation

detection feature is disabled.

Current-Sense Amplifier

An integrated current-sense amplifier magnifies

the voltage difference between the CSP input

pin and CSN input pin, which is outputted to the

CSO pin.

The

current-sense

amplifier

gain

is

programmed to one of four settings by an

external resistor connected between the CSG

pin and ground. Table 2 shows the current-

sense gain.

Table 2: Current-Sense Gain

RCSG

Gain

0Ω

210

10kΩ

105

30kΩ

52.5

100kΩ

21

The CSR pin creates a bias in the output

toward

a

positive

reference

voltage

corresponding

to

zero

current.

With

this

method, current can be measured in both

positive and negative directions.

The current-sense amplifier is typically used to

measure the voltage drop across an LS shunt

resistor. In some special applications, the

amplifier also measures the voltage drop across

the LS-FET by connecting the CSP input to the

drain of the LS-FET, and connecting CSN to

ground through blocking diodes (see Figure 2).

BST

CSP

GL

GH

OUT

CSN

Figure 2: Measure LS-FET Voltage Drop

CSEN is an output enable pin that disables the

current-sense amplifier

’s output. The CSEN pin

therefore allows multiple MP1922 devices to be

connected

to

a

single

analog-to-digital

converter (ADC) input, with one CSO output

enabled at a time to perform measurements.

To guarantee stability, the CSO pin should not

be loaded with capacitance above 100pF. The

CSO pin can drive about 500µA of output

current (IOUT).

Desaturation Detection

The voltage across both the HS-FET and LS-

FET is monitored by a circuit that compares the

voltage drop across the FET when it turns on to

a reference voltage.

Whenever a FET is turned on, there is a

blanking period, and then the voltage across

the FET is compared to the reference voltage. If

the FET voltage drop exceeds the reference,

then the outputs are disabled and the nFAULT

pin is driven active low.

The outputs remain disabled until the device is

disabled by de-asserting ENBL, removing VG,

or activating nSLEEP.

High-Side (HS) Gate Drive Generation

The HS gate drive voltage is typically generated

from CBST (connected between the OUT pin and

BST pin). Each time the LS-FET is turned on,

CBST is charged.

If the output is held high for a long period of

time (typically several seconds), then CBST

slowly discharges. This discharge eventually

results in the loss of the HS-FET gate drive.

To offset this leakage, an internal charge pump

generates a small current to maintain the CBST

charge. In some cases, especially at high

temperatures, this trickle current is not sufficient

to maintain the voltage on CBST.

The BST voltage (VBST) is monitored by an

under-voltage detection circuit. If the bootstrap

voltage falls below the VBST under-voltage

lockout (UVLO) threshold, then the MP1922

initiates a BST refresh cycle by briefly turning

off the HS-FET and turning on the LS-FET.

The auto-refresh behavior is controlled and

reported by the AR pin. The state of the AR pin

is sampled during start-up. If AR is connected

directly to ground, auto-refresh is enabled. If AR

is pulled up to a logic supply, then when VBST

falls below its UVLO threshold, the HS-FET is

disabled and the AR pin is pulled low. The

system

must

consequently

take

action

to

charge CBST by turning on the LS-FET or

initiating a new start-up cycle.