MP86952

– 70A INTELLI-PHASE™ SOLUTION WITH BUILT-IN MOSFETS AND DRIVERS

MP86952 Rev. 1.0

MonolithicPower.com

9

5/13/2021

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used by the controller to accurately monitor IIOUT.

The cycle-by-cycle current information from

IOUT is used for phase-current balancing, over-

current protection (OCP), and active voltage

positioning (output voltage droop).

Positive

and

Negative

Inductor

Current

Limits

If an HS-FET over-current (OC) condition is

detected, then the HS-FET turns off for one

PWM cycle. If an OC condition is detected for

eight consecutive cycles, then the HS-FET

latches off and the TOUT/FLT pin is pulled high

to VDD

’s voltage level. The LS-FET turns on

and remains on until ZCD, then turns off.

Recycle the power on VIN or VDD, or toggle EN

to release the latch and restart the device.

If a -35A valley current is detected, then the LS-

FET turns off and the HS-FET turns on for

200ns to limit the negative current. The LS-

FET

’s negative current limit does not trigger a

fault report.

Temperature-Sense

Output

with

Fault

Indicator (TOUT/FLT)

The TMON/FLT pin has dual functions. It acts

as the device’s junction temperature sense and

fault detection. These functions are described

below.

Junction Temperature Sense

If VDD exceeds its under-voltage lockout (UVLO)

threshold and the part is active, then the

TOUT/FLT pin voltage output is proportional to

the junction temperature (TJ). The gain is

8mV/°C with an 800mV offset at 25°C. For

example, TMON/FLT is 0.8V at TJ = 25°C, and

1.6V at TJ = 125°C.

Fault Function

When a fault occurs, TOUT/FLT is pulled to

VDD to report the fault event, regardless of TJ.

After a 200ns delay, PWM

’s resistance changes

according to the indicated fault event.

Table 2 shows the PWM resistance for each

fault event.

Table 2: PWM Resistance for Each Fault Event

Fault Event

PWM Resistance

Over-current (OC) fault

10k

Ω to AGND

Over-temperature (OT) fault

20k

Ω to AGND

SW to PGND short

1k

Ω to VDD

TMON/FLT monitors three different fault events:

OC, over-temperature (OT), and SW to PGND

short.

1.

OC fault: Eight consecutive current limit

faults trigger an OC fault. Once a fault

occurs, the part latches off to turn off the

HS-FET. The LS-FET turns on, then turns

off once IL reaches 0A. The PWM pin uses

a

10kΩ resistor connected to AGND to

indicate this fault event.

2.

OT fault: At TJ > 160°C, the part latches off

to turn off the HS-FET. The LS-FET turns

on, then turns off once IL reaches 0A. PWM

uses a

20kΩ resistor connected to AGND to

indicate this fault event.

3.

SW to PGND short: Once this fault occurs,

the part latches off to turn off the HS-FET.

PWM is pulled high via a

1kΩ resistor

connected to VDD to indicate this fault

event.

Release a fault latch by toggling EN, or cycling

the power on VIN or VDD.

For

multi-phase

operation,

connect

the

TOUT/FLT pin of each Intelli-

Phase™ together

(see Figure 3).

L1

PWM

Intelli- Phase

PWM1

L2

PWM

VIN

VIN

PWM2

TOUT/

FLT

VIN

VIN

TOUT/

FLT

Intelli-Phase

VOUT

COUT

Multi-Phase

Controller

Temperature

Analog-to-Digital

Converter

Intelli-Phase

Power Stage

Figure 3: Multi-Phase Temperature Sense