MP86952

– 70A INTELLI-PHASE™ SOLUTION WITH BUILT-IN MOSFETS AND DRIVERS

MP86952 Rev. 1.0

MonolithicPower.com

10

5/13/2021

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APPLICATION INFORMATION

PCB Layout Guidelines

Efficient

PCB

layout

is

critical

for

stable

operation. For the best results, refer to Figure 4

and follow the guidelines below:

1. Place the MLCC input capacitors as close to

VIN and PGND as possible.

2. Place the major MLCC capacitors on the

same layer as the MP86952.

3. Place

as

many

VIN

and

PGND

vias

underneath the package as possible. Place

these vias between the VIN and PGND long

pads.

4. Place a VIN copper plane on the second

inner

layer

to

form

the

PCB

stack

(positive/negative/positive)

to

reduce

parasitic impedance from the MLCC input

capacitor to the MP86952. Ensure that the

copper plane on the inner layer covers the

VIN vias and MLCC input capacitors.

5. Place more PGND vias close to the PGND

pin/pad to minimize parasitic resistance,

parasitic impedance, and thermal resistance.

6. Place the 0.1µF to 1µF BST capacitor and

the

VDRV

capacitor

as

close

to

the

MP86952

’s pins as possible.

7. For BST routing, use a trace width greater

than 20mils. Avoid placing vias on the BST

driving path.

8. Place the VDD decoupling capacitor close

to the device.

9. Connect AGND and PGND at the VDD

capacitor

’s ground connection.

10. Keep the IOUT signal trace away from high-

current paths, such as SW and PWM.

PGND

40

41

VIN

BST

IOUT

TOUT/FLT

EN

PWM

NC

SW

SW

SW

SW

SW

SW

SW

SW

SW

SW

NC

PHASE

NC

Figure 4: Recommended PCB Layout

Input Capacitor: 0402 Package (Top Side) and 0805 Package (Top Side and Bottom Side)

Inductor: 11mmx8mm Package

VDD/BST/VDRV Capacitors: 0402 Package

Via Size: 20/10mils