Data Sheet S15090EJ2V0DS

4

µµµµ PD16342

2. PIN FUNCTIONS

Symbol

Pin Name

I/O

Description

/LBLK

Low blanking

Input

/LBLK

= L: All output = L

/HBLK

High blanking

Input

/HBLK

= L: All output = H

/LE

Latch enable

Input

Latch on a falling edge

HZ

Output high impedance

Input

H: All output set to the high-impedance state

/CLR

Register clear

Input

L: All shift register data cleared to the L level

A1 to A3(6)

RIGHT data

I/O

Note

R,/L

= H, A1 to A3(6): Input, B1 to B3(6): Output

The parenthesized pins are used in 6-bit input mode.

B1 to B3(6)

LEFT data

I/O

Note

R,/L

= L, A1 to A3(6): Output, B1 to B3(6): Input

The parenthesized pins are used in 6-bit input mode.

CLK

Clock

Input

Shift on a rising edge

R,/L

Shift control

Input

H: Right shift mode

SR1: A1

→ S1.......S94 → B1 (SR2 and SR6 also shift in the same direction.)

Left shift mode

SR1: B1

→ S94.......S1 → A1 (SR2 and SR6 also shift in the same direction.)

IBS

Input mode switch

Input

H: 32-bit shift registers, 3-bit input mode

L: 16-bit shift registers, 6-bit input mode

O1 to O96

High withstand voltage

Output

80 V, +15/–30 mA MAX.

VDD1

Logic power supply

−

5 V

± 5%

VDD2

Driver power supply

−

15 to 70 V

VSS1

Logic ground

−

Connect to system ground

VSS2

Driver ground

−

Connect to system ground

Note In 3-bit input mode, unused I/O pins must be held at the L level.

To use for module, the back side of IC chip must be held at the VSS (GND) level.