Data Sheet S15090EJ2V0DS

5

µµµµ PD16342

3. TRUTH TABLE

Shift Register Block

Input

Output

R,/L

CLK

A

B

Shift Register

H

↑

Output

Note1

Right shift operation performed

HH or L

Input

Output

Hold

L

↑

Output

Note2

Left shift operation performed

L

H or L

Output

Input

Hold

Notes 1. On the rising edge of the clock, the data of S91 to S93 (S85 to S90) is shifted to S94 to S96 (S91 to S96), and is

output from B1 to B3 (B1 to B6) (The parenthesized pins are used in 6-bit input mode.).

2. On the rising edge of the clock, the data of S4 to S6 (S7 to S12) is shifted to S1 to S3 (S1 to S6), and is output

from A1 to A3 (A1 to A6) (The parenthesized pins are used in 6-bit input mode.).

Latch Block

/LE

Output State of Latch Section (/Ln)

↓

Latch Sn data

H or L

Hold latch (output) data

Driver Block

A (B)

/HBLK

/LBLK

HZ

Output State of Driver Block

x

L

H

L

All driver output: H

x

x

L

L

All driver output: L

x

x

x

H

All driver output: High Impedance

LH

H

L

L

HHH

L

H

Remark x: H or L, H: High level, L: Low level