82545EM GIGABIT ETHENET CONTROLLER SPECIFICATION UPDATE

24. Intermittent Issues with TCO Receive Packets in IPMI Mode

Problem:

The TCO Receive FIFO is implemented as a pair of buffers utilized in an alternating fashion. Under a specific

timing condition where a new packet arrives from the Ethernet for the TCO receive FIFO coincident with a

previous TCO packet being read from the FIFO to the SMBus, logic tracking the occupied/empty state of the

buffers can enter an inconsistent state. This problem does not occur if only a single TCO packet is passed

through the TCO Receive FIFO at a time.

Implication:

When the LAN controller is in this erratum state, symptoms may include (a) corrupted packets delivered to the

SMBus, (b) packets received to the SMBus twice, or (c) a received TCO packet appearing to be "stuck" in the

TCO Receive FIFO until a new TCO packet arrives. Most network operations are only mildly affected, as most

network protocols allow for lost or late packets and support header/payload integrity checksums.

Workaround(s):

To address this problem, a series of steps should be taken in BMC firmware:

•

First, the BMC firmware should check integrity of all TCO packets received by checking the IP/UDP

checksums and discarding any corrupted packets.

•

Second, the BMC firmware should implement a "check for erratum state" function using the following

conditions:

a) Check to see if two sequential packets received are exact duplicates.

b) Attempt to check for "stuck" packets to determine whether a packet received has simply been delayed

on the network versus "stuck" in the TCO Receive FIFO. The IPMI specification defines an 8 sequence-

number window; received TCO packets exceeding that window may be good indications of being “stuck”.

Depending upon application, BMC firmware may be able to implement additional mechanisms to detect

when a TCO packet received from the LAN controller appears to be one that had been given up as “lost”

on the network.

•

Finally, upon detecting a likely "TCO erratum state”, BMC firmware should implement a specific "TCO

Abort" operation on the SMBus to return the LAN controller from an erroneous state back to a normal,

operational state without requiring a LAN controller reset. A "TCO Abort" operation is an intentionally

abnormally terminated SMBus transaction. The specific TCO Abort transaction recommended by Intel

consists of an N-byte SMBus write (N>1) to the LAN controller where the BMC only provides 1 byte of data

before initiating a STOP.

Note that issuing this “TCO Abort” operation while the LAN controller is in a normal, healthy operational

state can in fact induce the erratum condition. Therefore, checks for the erratum condition should be

considered carefully so as to avoid excessive TCO Aborts while the LAN device is in a healthy state.

However, if the TCO Abort were to be errantly issued while the LAN controller is in a normal healthy state,

and the erratum state were to be induced, it is expected that the erratum-check criteria would again detect

& correct the state back to normal, healthy state.

Status:

Intel does not plan to resolve this erratum in a future stepping of the 82545EM Gigabit Ethernet Controller.

25. Message Signaled Interrupt Feature May Corrupt Write Transactions

Problem:

The problem is with the implementation of the Message Signaled Interrupt (MSI) feature in the Ethernet

controller. During MSI writes, the controller should use the MSI message data value in PCI configuration space.

At the same time, for normal write transactions (received packet data and/or descriptor writebacks), the

controller temporarily stores the data for write transactions in a small memory until it is granted ownership of the

PCI/PCI-X bus. The error condition occurs when during the MSI operation the controller incorrectly pulls data

from the memory storing the data waiting to be written. If there are any write transactions waiting when this

occurs, these transactions may become corrupted. This, in turn, may cause the network controller to lock up

and become unresponsive.

Implication:

If the affected products are used with an OS that utilizes Message Signal Interrupts and no accommodations are

made to mitigate the use of these interrupts, data integrity issues may occur.

Workaround:

For PCI systems, advertisement of the MSI capability can be turned off by setting the MSI Disable bit in the

EEPROM (Init Control Word 2, bit 7).

For PCI-X systems where MSI support is enumerated as part of the PCI-X specification, Intel is working with OS

vendors to ensure that any future implementations of their operating systems can detect these products and

avoid using the MSI mechanism. Further details will be communicated as they become available.

Status:

Intel does not plan to resolve this erratum in a future stepping of the 82545EM Gigabit Ethernet Controller.

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