82545EM GIGABIT ETHERNET CONTROLLER SPECIFICATION UPDATE

26. Link Establishment or Communication Problems in Fiber Mode When Link

Partner Does Not Fully Comply with the IEEE 802.3 Specification

Problem:

The following minor compliance issues have been discovered between the TBI/SERDES mode symbol

synchronization logic and the IEEE specification:

- When presented with short sequences of malformed code groups, the receive synchronization logic within the

Ethernet controller may acquire & indicate link/synchronization prematurely or incorrectly

-

When presented with certain short sequences of malformed code groups, the logic may retain

link/synchronization indication through the error sequence instead of immediately detecting and dropping

link/synchronization

- With some specific erroneous sequences of code groups, the auto-negotiation logic may establish link in

certain very specific situations where the specification says it should not

-

Finally, the receive error detection logic may not detect and count some symbol errors when malformed idle

patterns are received.

Implication:

If a link partner is not compliant with the IEEE 802.3 Specification in certain very specific ways, the 8254x

controller may not be able to establish link or communicate properly with it. If the controller is tested for strict

compliance with the IEEE 802.3 Specification, it may fail some of the Clause 36 and Clause 37 test cases.

However, Intel has performed extensive compatibility testing as an integral part of controller HW validation, and

continues to do so with the latest Ethernet devices. To date, these issues have not been shown to cause

interoperability problems with any Ethernet devices currently in production.

Workaround:

None.

Status:

Intel does not plan to resolve this erratum in a future stepping of the 82545EM Gigabit Ethernet Controller.

27. Wakeup Packet Memory (WUPM) cleared upon reset

Problem:

The 82545EM specifications state that the Wakeup Packet Memory (WUPM) is not cleared on any reset. This

is incorrect. Any reset or power-state transition will clear the contents of these registers.

Implication:

Because a power-state transition takes place on wakeup, the Wakeup Packet Memory will always be cleared

before it can be read by software.

This makes the memory effectively unable to provide the capability for

inspecting the wakeup packet content.

Workaround:

There is no workaround. WUPM will be considered to be defeatured for the affected controllers.

Status:

Intel does not plan to resolve this erratum in a future stepping of the 82545EM Gigabit Ethernet Controller.

28. Unexpected RCMP ACK packets in ASF mode

Problem:

According to the RMCP protocol, the response to all RMCP commands (except ACK) should be an RMCP ACK

packet. In ASF mode, the Ethernet Controller responds to RMCP ACK packets with a second ACK.

Implication:

Any management software should be aware of this behavior and not respond to the additional RMCP ACK

packets.

Workaround:

None.

Status:

Intel does not plan to resolve this erratum in a future stepping of the 82545EM Gigabit Ethernet Controller.

29. Exceeding PCI Power Management Specification Limit of 375mA current

during reset and power state transitions

Problem:

During resets and power state transitions the controller may briefly draw more than 375 mA of current as the

digital signal processors in the PHY attempt to converge. The excessive current draw persists for approximately

100 milliseconds. Refer to the "Power Specifications -- MAC/PHY" section of this document for specific values.

Implication:

If an application has current limiting circuitry in place, the Ethernet Controller may trigger these safeguards in

power-up or during transitions between D0 and D3 power states.

Workaround:

None.

Status:

Intel does not plan to resolve this erratum in a future stepping of the 82545EM Gigabit Ethernet Controller.

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