MPC850 datasheet(30/68 Pages) MOTOROLA

30 / 68 page

MPC850 (Rev. A/B/C) Hardware Speciﬁcations

MOTOROLA

Layout Practices

Figure 20 provides the timing for the asynchronous external master memory access controlled by the

GPCM.

Figure 20. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00)

Figure 21 provides the timing for the asynchronous external master control signals negation.

Figure 21. Asynchronous External Master—Control Signals Negation Timing

Table 7 provides interrupt timing for the MPC850.

Table 7. Interrupt Timing

Num

Characteristic 1

The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being deﬁned as

level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference

to the CLKOUT.

The timings I41, I42, and I43 are speciﬁed to allow the correct function of the IRQ lines detection circuitry, and has no

direct relation with the total system interrupt latency that the MPC850 is able to support

50 MHz

66MHz

80 MHz

Unit

Min

Max

Min

Max

Min

Max

I39

IRQx valid to CLKOUT rising edge (set up time)

6.00

—

6.00

—

6.00

—

I40

IRQx hold time after CLKOUT.

2.00

—

2.00

—

2.00

—

I41

IRQx pulse width low

3.00

—

3.00

—

3.00

—

I42

IRQx pulse width high

3.00

—

3.00

—

3.00

—

I43

IRQx edge-to-edge time

80.00

—

121.0

—

100.0

—

CLKOUT

A[6:31],

TSIZ[0:1],

R/W

CSx

B39

B40

B22

CSx, WE[0:3],

OE, GPLx,

BS[0:3]

B43

MPC850 Datasheet(PDF) 30 Page - Motorola, Inc

MPC850 Datasheet(HTML) 30 Page - Motorola, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

Datasheet Download

Link URL