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UPD17062 Datasheet(PDF) 137 Page - Renesas Technology Corp |
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UPD17062 Datasheet(HTML) 137 Page - Renesas Technology Corp |
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137 / 298 page ![]() 135 µPD17062 Fig. 12-2 Relationship Between the Timer Mode Select Register and Timer Interval Set Pulse b3 b2 b1 b0 B T M 0 Z X B T M 0 C K 2 B T M 0 C K 1 B T M 0 C K 0 09H R/W Read/Write 000 001 010 011 100 101 110 111 0 1 10 Hz ( 100 ms) 200 Hz ( 5 ms) 10 Hz ( 100 ms) 200 Hz ( 5 ms) fTMIN/5 Hz (5/fTMIN s) 200 Hz ( 5 ms) fTMIN/6 Hz (6/fTMIN s) 200 Hz ( 5 ms) 200 Hz ( 5 ms) 10 Hz ( 100 ms) 50 Hz ( 20 ms) 50 Hz ( 20 ms) 200 Hz ( 5 ms) fTMIN/5 Hz (5/fTMIN s) 200 Hz ( 5 ms) fTMIN/6 Hz (6/fTMIN s) 200 Hz 50 Hz fTMIN/6 (Hz) 10 Hz fTMIN/5 (Hz) Control register Register Address Bit Flag symbol Timer mode select (BTM0CK) Selection of frequency (time) of the timer carry FF set pulse Selection of frequency (time) of the timer interrupt pulse Internal timer Internal timer Internal timer Internal timer External timer Internal timer External timer Internal timer Internal timer Internal timer Internal timer Internal timer Internal timer External timer Internal timer External timer fTMIN is the input frequency (50 or 60 Hz) at the P0B2/TMIN pin. Disables the bias circuit. Enables the bias circuit. Duty cycle Duty cycle 80 ms 1 ms 5 ms 4 ms 100 ms 20 ms 20% 80% 50% 10 ms 20 ms 10 ms 50% |
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