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UPD17062 Datasheet(PDF) 154 Page - Renesas Technology Corp |
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UPD17062 Datasheet(HTML) 154 Page - Renesas Technology Corp |
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154 / 298 page  152 µPD17062 In reality, however, to avoid skipping the timer process in the above example, a delay is provided between the negative-going edge of the timer carry FF set pulse and the negative-going edge of the timer interrupt pulse, as shown in Fig. 12-10 (b). As shown at (2) in Fig. 12-10, restricting the clock process to within 10 ms can eliminate skipping of a timer interrupt that would otherwise be caused by a CE reset. Fig. 12-10 Timing Chart (a) (b) CE pin Timer carry FF set pulse Timer interrupt pulse Timer interrupt Because the timer carry FF set pulse goes high, a CE reset occurs here, thus skipping detection of a timer interrupt once. CE pin Timer carry FF set pulse Timer interrupt pulse Timer interrupt Timer interrupt Delay; 10 ms in this case CE reset Because there is a delay of 10 ms between the negative-going edge of the timer interrupt pulse and the positive-going edge of the timer carry FF set pulse, a CE reset does not hamper the normal timer processing, provided that the timer interrupt handling is finished within 10 ms. |
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