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UPD17062 Datasheet(PDF) 155 Page - Renesas Technology Corp |
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UPD17062 Datasheet(HTML) 155 Page - Renesas Technology Corp |
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155 / 298 page  153 µPD17062 13. STANDBY The standby function is intended to reduce the current drain of the device at backup. 13.1 STANDBY BLOCK CONFIGURATION Fig. 13-1 shows the configuration of the standby block. As shown in Fig. 13-1, the standby block is further divided into halt control and clock stop control blocks. The halt control block consists of the halt control circuit, interrupt control block, timer carry FF, and the P0D0/ ADC2 to P0D3/ADC5 pins. It controls the operation of the CPU (program counter, instruction decoder, and ALU block). The clock stop control block controls the 8 MHz crystal oscillator, CPU, system register, and control register. Fig. 13-1 Standby Block Configuration ALU Halt block Interrupt block Timer carry FF Halt control circuit HALT h P0D3/ADC5 pin P0D2/ADC4 pin P0D1/ADC3 pin P0D0/ADC2 pin Program counter (PC) Instruction decoder Clock stop block System register CE pin Clock stop control circuit STOP s Control register XOUT pin XIN pin Internal clock CPU |
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