UPD17062 datasheet(199/298 Pages) RENESAS

199 / 298 page

197

µPD17062

15.3.6

Notes on Using I/O Ports (P0A1 and P0A0)

As shown in the example below, when pins P0A1 and P0A0 pins are used as output pins, the contents of

the output latch may be overwritten.

Example:

INITFLG

NOT P0ABIO3, NOT P0ABIO2, P0ABIO1, P0ABIO0

; Set the P0A1, P0A0 pins as output pins

INITFLG

NOT P0A3, NOT P0A2, P0A1, P0A0

;

; Output a high level signal to the P0A1 and P0A0 pins

CLR1

P0A1

; Output a low level signal to the P0A1 pin

; Macro expansion

AND .MF.P0A1 SHR 4, #.DF. (NOT P0A1 AND 0FH)

If the P0A0 pin is externally pulled down to the low level upon execution of instruction

#, above,

the CLR1 instruction overwrites the contents of the output latch of the P0A0 pin with 0.

15.3.7

State of I/O Port (P0A, P0B, P1B, P1C) at Reset

(1) At power-on reset

All I/O ports are set as input ports.

Since the contents of the output latch are “indefinite”, the output latch must be initialized by the program

before the ports can be switched to output ports.

(2) At CE reset

All I/O ports are set as input ports.

The contents of the output latch are retained.

(3) At clock stop

All I/O ports are set as input ports.

The contents of the output latch are retained.

In I/O ports other than P1C, the RESET signal output at clock stop prevents the current drain from being

increased by noise from the input buffer, as shown in Section 15.3.1.

(4) During the halt state

The previous state is retained.

UPD17062 Datasheet(PDF) 199 Page - Renesas Technology Corp