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UPD17062 Datasheet(PDF) 217 Page - Renesas Technology Corp |
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UPD17062 Datasheet(HTML) 217 Page - Renesas Technology Corp |
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217 / 298 page  215 µPD17062 16.6 SERIAL INTERFACE INTERRUPT SOURCE REGISTER (SIO0IMD) The interrupt source register (SIO0IMD) is a four-bit register that specifies when an interrupt is generated in the CPU during serial interface communication. The SIO0IMD register is mapped to address 38H of the register file. Fig. 16-6 shows the configuration of the SIO0IMD register. The register is not mapped to the two high-order bits of the SIO0IMD. If the two high-order bits of the SIO0IMD are read, 0 is read from each bit. Fig. 16-6 Configuration of Serial Interface Interrupt Source Register (RF: 38H) Table 16-9 Functions of Serial Interface Interrupt Source Register SIO0IMD1 SIO0IMD0 Function 0 0 An interrupt request is generated when the 7th bit of the shift clock rises. 0 1 An interrupt request is generated when the 8th bit of the shift clock falls. 1 0 An interrupt request is generated at the rising edge of the 7th bit of the shift clock immediately after detection of the start condition. 1 1 An interrupt request is generated upon detection of the stop condition. Bit position b3 b2 b1 b0 Flag name SIO0IMD3 SIO0IMD2 SIO0IMD1 SIO0IMD0 (0) (0) |
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