 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
UPD17062 Datasheet(PDF) 218 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
UPD17062 Datasheet(HTML) 218 Page - Renesas Technology Corp |
|
|
218 / 298 page  216 µPD17062 Bit position b3 b2 b1 b0 Flag name SIO0CK3 SIO0CK2 SIO0CK1 SIO0CK0 (0) (0) SIO0CK1 SIO0CK0 Internal clock frequency 0 0 100 kHz 0 1 200 kHz 1 0 500 kHz 1 1 1 MHz 16.7 SHIFT CLOCK FREQUENCY REGISTER (SIO0CK) The shift clock frequency register is a four-bit register for setting the frequency of the internal clock of the serial interface. The shift clock frequency register is mapped to address 39H of the register file. Fig. 16-7 shows the configuration of the shift clock frequency register. The register is not mapped to the two high-order bits of the shift clock frequency register. If the two high-order bits of the shift clock frequency register are read, 0 is read from each bit. Fig. 16-7 Configuration of Shift Clock Frequency Register (RF: 39H) Table 16-10 Internal Clock Frequencies of Serial Interface |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
