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UPD17062 Datasheet(PDF) 223 Page - Renesas Technology Corp |
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UPD17062 Datasheet(HTML) 223 Page - Renesas Technology Corp |
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223 / 298 page  221 µPD17062 18.3 PROGRAMMABLE DIVIDER (PD) AND PLL MODE SELECT REGISTER 18.3.1 Programmable Divider Configuration Fig. 18-2 shows the configuration of the programmable divider (PD). As shown in Fig. 18-2, the programmable divider consists of a swallow counter and programmable counter. Fig. 18-2 Programmable Divider Configuration 0CH 0DH 0EH 0FH DBF3 DBF2 DBF1 DBF0 M S B L S B 16 12 4 PSC VCO Data buffer (DBF) Address Symbol Data PLL data register 12 bits 4 bits Swallow counter 4 bits Programmable counter 12 bits fN To -DET φ 1/2 frequency divider PLL disable signal |
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