UPD17062 datasheet(227/298 Pages) RENESAS

227 / 298 page

225

µPD17062

18.5

PHASE COMPARATOR (

φ-DET), CHARGE PUMP, AND UNLOCK DETECTION BLOCK

18.5.1

Configuration of the Phase Comparator (

φ-DET), Charge Pump, and Unlock Detection Block

Fig. 18-5 shows the configuration of the phase comparator (

φ-DET), charge pump, and unlock detection

block.

The phase comparator compares the phase of the output frequency “fN” of the programmable divider (PD)

with the reference frequency output “fr” of the reference frequency generator, and outputs the up request

signal (UP) or down request signal (DW).

The charge pump directs the output of the phase comparator to the error output pin (EO pin).

The unlock detection block consists of a delay control circuit and unlock flip-flop (FF). It detects the unlock

state of the PLL frequency synthesizer.

Sections 18.5.2, 18.5.3, and 18.5.4 explain the operation of the phase comparator, charge pump, and unlock

detection block, respectively.

Fig. 18-5

Configuration of the Phase Comparator, Charge Pump, and Unlock Detection Block

32H

22H

b1 b0

b2 b1

Control register

VDD

P-ch

N-ch

Address

Bit

Flag

symbol

Unlock detection block

Delay control

Unlock FF

Charge pump

Reference

frequency

generator

Programmable

divider

PLL disable signal

Phase comparator ( -DET)

UPD17062 Datasheet(PDF) 227 Page - Renesas Technology Corp

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