 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
UPD17062 Datasheet(PDF) 231 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
UPD17062 Datasheet(HTML) 231 Page - Renesas Technology Corp |
|
|
231 / 298 page  229 µPD17062 (1) PLL unlock FF judge register (PLLULJDG) This register is a read-only register. It is reset when its content is read into a window register (WR) with a PEEK instruction. Because the unlock FF is set at intervals of the period (1/fr) of the reference frequency fr, the content of this register must be read into the window register at intervals larger than the period of the reference frequency. Fig. 18-7 Configuration and Functions of the PLL Unlock FF Judge Register (PLLULJDG) Remark The PLLULJDG is reset when it is read-accessed with a PEEK instruction. Register Flag symbol b3 b2 b1 b0 P L L U L 22H R Address Read/write Power-on Clock stop CE 00 0 1 Detects the state of the unlock FF. Unlock FF = 0 : PLL locked Unlock FF = 1 : PLL unlocked 0 * 0 Fixed to 0. PLL unlock FF judge register (PLLULJDG) 0 0 * Undefined Hold Hold |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
