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UPD17062 Datasheet(PDF) 232 Page - Renesas Technology Corp |
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UPD17062 Datasheet(HTML) 232 Page - Renesas Technology Corp |
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232 / 298 page  230 µPD17062 (2) PLL unlock FF delay control register (PLULSEN) When the unlock FF disable mode is selected, the unlock FF remains set. So, note that if the PLL unlock FF judge register checks the unlock FF in the unlock FF disable mode, it always appears to be unlocked (PLLUL flag = 1). Fig. 18-8 Configuration and Functions of the PLL Unlock FF Delay Control Register (PLULSEN) P L U L S E N 3 Register Flag symbol b3 b2 b1 b0 P L U L S E N 1 P L U L S E N 0 32H R/W Address Read/write 0 Power-on Clock stop CE 00 0 01 10 11 1.25-1.5 s or more 3.5-3.75 s or more 0.25-0.5 s or more Unlock FF disabled (Always to be set) 00 00 Hold Sets the delay time between the reference (fr) and division frequency (fN) signals, which is necessary to set the unlock FF. Fixed to 0. PLL unlock FF delay control (PLULSEN) Hold P L U L S E N 2 µ µ µ |
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