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VSC6250 Datasheet(PDF) 1 Page - Vitesse Semiconductor Corporation

Part # VSC6250
Description  1Gb/s 16-Channel Drive-Side Deskew IC
PDF  18 Pages
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Manufacturer  VITESSE [Vitesse Semiconductor Corporation]
Direct Link  http://www.vitesse.com
Logo VITESSE - Vitesse Semiconductor Corporation

VSC6250 Datasheet(HTML) 1 Page - Vitesse Semiconductor Corporation

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G52197-0, Rev. 4.0
© VITESSE SEMICONDUCTOR CORPORATION
Page 1
8/19/00
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC6250
1Gb/s 16-Channel
Drive-Side Deskew IC
Features
Applications
General Description
The VSC6250 is intended for use in the next generation of high-speed, high-accuracy memory testers for
devices such as Direct RAMBUS DRAM, SLDRAM, DDR SDRAM, and fast SSRAM.
The VSC6250 provides ultra-precise timing to allow next generation memory testers to achieve excellent
overall timing accuracy. Timing delays of the VSC6250 are extremely stable with respect to temperature and
voltage. Proprietary circuit design and process technology reduce pattern, data, frequency, and duty-cycle
dependencies to an absolute minimum. The VSC6250 requires no external DACs, which eliminates errors due
to DAC reference noise and analog crosstalk, and DAC temperature and voltage drift. The VSC6250 is avail-
able in a 128-pin PQFP, 14x20mm thermally-enhanced package.
• Wide Span: > 4ns Usable Range
• Pulse Width Adjustment to Compensate for
Dispersion in Pin Electronics:
± 2ns Independent Adjustment of Rising and
Falling Edges
• Fully Digital Single-Chip Solution:
No Off-Chip DACs Required
No DAC-Induced Timing Errors from Analog
Crosstalk, Reference Noise, Temperature, or
Voltage Drift
• Single Power Supply: -2V @ 5W
• 128-Pin PQFP, 14x20mm Thermally-
Enhanced Package
• High-Speed Operation:
1 Gb/s Data Rate
500ps min Output Pulse Width
750ps min Input Pulse Width
• Excellent Overall Timing Accuracy:
Ultra-Stable Timing Delays
Minimum Pattern Dependence
Very Fine Timing Resolution (1 LSB = 8ps)
• High Level of Integration Reduces Board Area:
16 Independently Adjustable Delay Lines in a
Single Package
• Configurable as 2 1:8 or 1:16
• High-Speed Instrumentation: Pulse Generators,
Timing Margin Testers for Datalink, Interface,
and Disk Drive Applications
• Telecom, Datacom, and Computer Deskew
• Drive-Side Deskew in High-Speed Memory
Testers
• Direct RAMBUS DRAM, SLDRAM, DDR
SDRAM, Fast SSRAM


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