RT8097D

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is a registered trademark of Richtek Technology Corporation.

DS8097D-07

June

2021

www.richtek.com

13

Inductor saturation current should be chosen over IC’s

current limit.

Input Capacitor Selection

High quality ceramic input decoupling capacitor, such

as X5R or X7R, with values greater than 22

µF are

recommended for the input capacitor. The X5R and

X7R ceramic capacitors are usually selected for power

regulator capacitors because the dielectric material has

less capacitance variation and more temperature

stability.

Voltage rating and current rating are the key parameters

when selecting an input capacitor. Generally, selecting

an input capacitor with voltage rating 1.5 times greater

than the maximum input voltage is a conservatively safe

design.

The input capacitor is used to supply the input RMS

current, which can be approximately calculated using

the following equation :

OUT

OUT

IN_RMS

LOAD

IN

IN

VV

I

= I

1

VV





×

×−









The next step is selecting a proper capacitor for RMS

current rating. One good design uses more than one

capacitor with low equivalent series resistance (ESR) in

parallel to form a capacitor bank.

The input capacitance value determines the input ripple

voltage of the regulator. The input voltage ripple can be

approximately calculated using the following equation :

OUT(MAX)

OUT

OUT

IN

IN

SW

IN

IN

I

VV

V

=

1

Cf

V

V





∆

×

×−





×





Output Capacitor Selection

The output capacitor and the inductor form a low pass

filter in the Buck topology. In steady state condition, the

ripple current flowing into/out of the capacitor results in

ripple voltage. The output voltage ripple (VP-P) can be

calculated by the following equation :

P_P

LOAD(MAX)

OUT

SW

1

V

= LIR I

ESR +

8C

f





×× 



××





When load transient occurs, the output capacitor

supplies the load current before the controller can

respond. Therefore, the ESR will dominate the output

voltage sag during load transient. The output voltage

undershoot (VSAG) can be calculated by the following

equation :

SAG

LOAD

V

= I

ESR

∆

×

For a given output voltage sag specification, the ESR

value can be determined.

Another parameter that has influence on the output

voltage sag is the equivalent series inductance (ESL).

The rapid change in load current results in di/dt during

transient. Therefore, the ESL contributes to part of the

voltage sag. Using a capacitor with low ESL can obtain

better transient performance. Generally, using several

capacitors connected in parallel can have better

transient performance than using a single capacitor for

the same total ESR.

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature.

The maximum power dissipation can be calculated by

the following formula :

PD(MAX) = (TJ(MAX) − TA) / θJA

where TJ(MAX) is the maximum junction temperature, TA

is the ambient temperature, and

θJA is the junction to

ambient thermal resistance.

For recommended operating condition specifications,

the maximum junction temperature is 125

°C. The

junction to ambient thermal resistance,

θJA, is layout

dependent.

For

SOT-23-5 package,

the thermal

resistance,

θJA, is 97.8°C/W on a two -layer thermal test

board. For SOT-23-6 package, the thermal resistance,

θJA, is 91.5°C/W on a two-layer thermal test board. The

maximum power dissipation at TA = 25°C can be

calculated by the following formula :

PD(MAX) = (125°C − 25°C) / (97.8 °C/W) = 1.02W for

SOT-23-5 package

PD(MAX) = (125°C − 25°C) / (91.5°C/W) = 1.09W for

SOT-23-6 package

The maximum power dissipation depends on the

operating ambient temperature for fixed TJ(MAX) and

thermal resistance,

θJA. The derating curve in Figure 2

allows the designer to see the effect of rising ambient