MA5104

6

Figure 12: Write Cycle

1.

WE must be high during all address transitions.

of the write cycle.

4. If the

CS low transition occurs simultaneously with, or after, the WE low transition, the output remains in

the high impedance state.

5. DATA OUT is the write data of the current cycle, if selected.

6. DATA OUT is the read data of the next address,if selected.

ADDRESS

(7)

(4)

WE

DATA OUT

(5)

(6)

HIGH

IMPEDANCE

DATA VALID

DATA IN

CS