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SN65MLVD047 Datasheet(PDF) 12 Page - Texas Instruments

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Part # SN65MLVD047
Description  MULTIPOINT-LVDS QUAD DIFFERENTIAL LINE DRIVER
PDF  17 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

SN65MLVD047 Datasheet(HTML) 12 Page - Texas Instruments

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APPLICATION INFORMATION
Multipoint Configuration
Multidrop Configuration
D
Zt
Zt
Zt
D
Unused Channel
Live Insertion/Glitch Free Power Up/Down
SN65MLVD047
SLLS606A – MARCH 2004 – REVISED JULY 2005
The SN65MLVD047 is designed to allow multipoint communication on a shared bus.
Multipoint is a bus configuration with multiple drivers and receivers present. An example is shown in Figure 17.
The figure shows transceivers interfacing to the bus, but a combination of drivers, receivers, and transceivers is
also possible. Termination resistors need to be placed on each end of the bus, with the termination resistor value
matched to the loaded bus impedance.
Figure 17. Multipoint Architecture
Multidrop configuration is similar to multipoint configuration, but only one driver is present on the bus. A multidrop
system can be configured with the driver at one end of the bus, or in the middle of the bus. When a driver is
located at one end, a single termination resistor is located at the far end, close to the last receiver on the bus.
Alternatively, the driver can be located in the middle of the bus, to reduce the maximum flight time. With a
centrally located driver, termination resistors are located at each end of the bus. In both cases the termination
resistor value should be matched to the loaded bus impedance. Figure 18 shows examples of both cases.
Figure 18. Multidrop Architectures With Different Driver Locations
The SN65MLVD047 is designed to allow multipoint communication on a standard bus. A 360-k
Ω pull-down
resistor is built in every LVTTL input. The unused driver inputs and outputs may be left floating.
During a live insertion event or a power cycle the outputs of the SN65MLVD047 leave the high impedance state
and possibly glitch the bus. Specifically when the VCC applied to the device is between 1.3 and 2.0 VDC the
output state (high or low) of the device reflects the input level at the corresponding A pin.
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