ES9080Q datasheet(24/146 Pages) ESS

24 / 146 page

CONFIDENTIAL ADVANCE INFORMATION 0.4.3

ES9080 Product Datasheet

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM

The following list shows the various clocks of the ES9080 and the associated registers for configuration.

Analog DAC Clock

•

Reg 5 (ANALOG_DAC_ENABLE)

•

Reg 193[7] (PLL_BYP)

•

Reg 193[2:1] (SEL_PLL_IN)

•

Reg 193[0] (EN_PLL_CLKIN)

NSMOD Clock

The NSMOD clock is utilized by the HyperStream® II Noise Shaped MODulators.

•

Reg 1[7:4] (ENABLE_NSMOD_CHxx)

•

Reg 1[3:0] (ENABLE_DAC_CHxx)

•

Reg 193[7] (PLL_BYP)

•

Reg 193[1] (SEL_PLL_IN)

•

Reg 193[0] (EN_PLL_CLKIN)

DAC Interpolation Path Clock

•

Reg 3[5:0] (SELECT_IDAC_NUM)

•

Reg 1[3:0] (ENABLE_DAC_CHxx)

•

Reg 193[7] (PLL_BYP)

•

Reg 193[1] (SEL_PLL_IN)

•

Reg 193[0] (EN_PLL_CLKIN)

Master BCK and WS

•

Reg 78 (MASTER MODE CONFIG)

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Reg 79[6:4] (MASTER_WS_SCALE)

•

Reg 4[6:0] (SELECT_MENC_NUM)

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Reg 1[3:0] (ENABLE_DAC_CHxx)

•

Reg 193[7] (PLL_BYP)

•

Reg 193[1] (SEL_PLL_IN)

•

Reg 193[0] (EN_PLL_CLKIN)

DSD Clock

•

Reg 2[1] (ENABLE_DSD_DECODE)

TDM Clock

•

Reg 2[0] (ENABLE_TDM_DECODE)

DoP Clock

•

Reg 2[2] (ENABLE_DOP_DECODE)

•

Reg 2[0] (ENABLE_TDM_DECODE)

S/PDIF

•

Reg 3[7] (ENABLE_SPDIF_ENCODE)

•

Reg 1[3:0] (ENABLE_DAC_CHxx)

•

Reg 193[7] (PLL_BYP)

•

Reg 193[1] (SEL_PLL_IN)

•

Reg 193[0] (EN_PLL_CLKIN)

ES9080Q Datasheet(PDF) 24 Page - ESS Technology,Inc

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