ES9080Q datasheet(28/146 Pages) ESS

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CONFIDENTIAL ADVANCE INFORMATION 0.4.3

ES9080 Product Datasheet

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM

Analog Features

APLL

The ES9080 features a built-in Analog PLL (APLL) for generating arbitrary system clock frequencies (Fout) when no dedicated external clock is

available. The APLL employs a fractional feedback divider to produce virtually any input/out frequency combination.

Figure 9 - Functional Block Diagram of ES9080 APLL

The following equation describes the relationship between input frequency (Fin) and output frequency (Fout) of the APLL:

�� = (

��

) ∗

��

The divider ratios are configured using the synchronous I2C register interface using while observing the constraints on the reference (Fref) and VCO

frequencies (Fvco):

�� = (

��

)

0.70�� < �� < 1.25��

�� = �� ∗ ��

90�� < �� < 100��

The divider ratios are set using the synchronous I2C interface:

a. Ni = input dividing ratio. Reg 202-200[9:1], PLL_CLK_IN_DIV

b. Nfb = feedback dividing ratio. The feedback divider ratio is a 24 bit fractional value to achieve a high resolution output frequency and is

calculated using:

�� =

225

��

FBDIV is accessible in Reg 199-197[23:0], PLL_CLK_FB_DIV

No = output dividing ratio. Reg 202-200[18:10], PLL_CLK_OUT_DIV

GPIO1/MCLK

DATA_CLK

REG 1V8

NFB

REG 1V2

FOUT

PLL Bypass

ES9080Q Datasheet(PDF) 28 Page - ESS Technology,Inc