AD9549 datasheet(50/78 Pages) AD

50 / 78 page

AD9549

Preliminary Technical Data

Rev. PrA | Page 50 of 78

cases, the status flags are monitored for a change of state in

either direction (see the diagram below).

Whether or not a particular state change is allowed to generate

an IRQ is dependent on the state of the bits in the IRQ Mask

which are to constitute cause for an IRQ. If an unmasked event

occurs, it will trigger the IRQ latch and the IRQ Flag will be

asserted (active high). The state of the IRQ Flag is made

available externally via one of the programmable status pins

(see the Status Pins section of this document).

The automatic assertion of the IRQ Flag causes the contents of

the Status Register to be transferred to the IRQ Register. The

user can then read the IRQ Register any time after the

indication of an IRQ event (i.e., assertion of the IRQ Flag). By

noting the bits in the IRQ Register that is set, the cause of the

IRQ event can be determined.

Once the IRQ Register has been read, the user must set the IRQ

Reset bit in the appropriate control register via the serial I/O

port. This restores the IRQ Flag to its default state, clears the

IRQ status register, and resets the edge detection logic that

monitors the status flags in preparation for the next state

change.

Status

Flags

Status Register

Edge

Detect

Edge

Detect

Edge

Detect

Edge

Detect

Edge

Detect

Edge

Detect

Edge

Detect

Edge

Detect

Edge

Detect

Edge

Detect

Edge

Detect

IRQ Mask Register

IRQ

Reg.

IRQ Reset

Figure 36: Interrupt Request Logic

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