AD9549 datasheet(54/78 Pages) AD

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AD9549

Preliminary Technical Data

Rev. PrA | Page 54 of 78

There are three types of registers on the AD9549: buffered, live,

and read-only. Buffered (also referred to as mirrored) registers

require an IO_UPDATE to transfer the new values from a

temporary buffer on the chip to the actual register, and are

marked with an “M” in the column labeled “Type” of the

the Register Update bit (R05h<0>) will cause the update to

occur. Since any number of bytes of data can be changed before

issuing an update command, the update simultaneously enables

all register changes since any previous update. Live registers do

not require IO_UPDATE and update immediately after being

written. Read-only registers ignore write commands, and are

marked “RO” in the “Type” column of the register map. The

“Type” column of the register map may also have an “AC,”

which indicates that the register is auto-clearing.

Read

If the instruction word is for a read operation (I15 = 1b), the

next N × 8 SCLK cycles clock out the data from the address

specified in the instruction word, where N is 1,2,3,4 as

determined by W1:W0. In this case, 4 is used for streaming

mode where 4 or more words are transferred per read. The data

read back is valid on the falling edge of SCLK.

The default mode of the AD9549 serial control port is

bidirectional mode, and the data read back appears on the

SDIO pin. It is possible to set the AD9549 to unidirectional

mode by writing the SDO enable register at 00h<7> = 0b, and in

that mode, the requested data appears on the SDO pin.

By default, a read request reads the register value that is

currently in use by the AD9549. However, setting R04h<0>=1

will cause the “buffered” registers to be read instead. The

buffered registers are the ones that will take effect during the

next IO_UPDATE.

SCLK

SDIO

SDO

CSB

UPDATE

REGISTERS

toggle

IO_UPDATE

SERIAL

CONTROL

PORT

AD9549

CORE

Figure 38: Relationship Between Serial Control Port Register Buffers

and Control Registers of the AD9549

The AD9549 uses Addresses 00h to 509h. Although the

AD9549 serial control port allows both 8-bit and 16-bit

instructions, the 8-bit instruction mode provides access to five

address bits (A4 to A0) only, which restricts its use to the

address space 00h to 01F. The AD9549 defaults to 16-bit

instruction mode on power-up, and the 8-bit instruction mode

is not supported.

THE INSTRUCTION WORD (16 BITS)

The MSB of the instruction word is R/W, which indicates

whether the instruction is a read or a write. The next two bits,

W1:W0, indicate the length of the transfer in bytes. The final 13

bits are the address (A12:A0) at which to begin the read or write

operation.

For a write, the instruction word is followed by the number of

bytes of data indicated by Bits W1:W0, which is interpreted

according to Table 6.

A12:A0

: These 13 bits select the address within the register map

that is written to or read from during the data transfer portion

of the communications cycle. The AD9549 uses all of the 13-bit

address space. For multi-byte transfers, this address is the

starting byte address.

Bytes to Transfer

(excluding the two-byte instruction)

Streaming Mode

Table 6: Byte Transfer Count

MSB/LSB FIRST TRANSFERS

The AD9549 instruction word and byte data may be MSB first

or LSB first. The default for the AD9549 is MSB first. The LSB

first mode may be set by writing 1b to Register 00h<6>, and

requires that an I/O Update be executed. Immediately after the

LSB, first bit is set, all serial control port operations are changed

to LSB first order.

When MSB first mode is active, the instruction and data bytes

must be written from MSB to LSB. Multi-byte data transfers in

MSB first format start with an instruction byte that includes the

data bytes must follow in order from high address to low

address. In MSB first mode, the serial control port internal

address generator decrements for each data byte of the multi-

byte transfer cycle.

AD9549 Datasheet(PDF) 54 Page - Analog Devices

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