SP6133 datasheet(5/20 Pages) SIPEX

5 / 20 page

Oct 24-06 Rev L

SP633 Synchronous Buck Controller

PIN DESCRIPTION

THEORY OF OPERATION

General Overview

TheSP6133isafixedfrequency,voltage

mode, synchronous PWM controller opti-

mizedforhighefficiency.Theparthasbeen

designedtobeespeciallyattractiveforsingle

supply input voltages ranging between 5V

and 24V.

The heart of the SP633 is a wide bandwidth

transconductanceamplifierdesignedtoac-

commodate Type II and Type III compensa-

tion schemes. A precision 0.8V reference

present on the positive terminal of the error

amplifierpermitstheprogrammingofthe

output voltage down to 0.8V via the VFB pin.

The output of the error amplifier, COMP,

compared to a V peak-to-peak ramp is

responsible for trailing edge PWM control.

ThisvoltagerampandPWMcontrollogicare

governed by the internal oscillator that ac-

curatelysetsthePWMfrequencyto300kHz.

NAME

DESCRIPTION

High current driver output for the low side NFET switch. It is always low if GH is high or during

a fault. Resistor pull down ensures low state at low voltage.

PGND Ground Pin. The power circuitry is referenced to this pin. Return separately from other ground

traces to the (-) terminal of Cout.

GND Ground pin. The control circuitry of the IC is referenced to this pin.

VFB

FeedbackVoltageandShortCircuitDetectionpin.ItistheinvertinginputoftheErrorAmplifier

and serves as the output voltage feedback point for the Buck Converter. The output voltage is

sensed and can be adjusted through an external resistor divider. Whenever VFB drops 0.25V

below the positive reference, a short circuit fault is detected and the IC enters hiccup mode.

COMP

OutputoftheErrorAmplifier.Itisinternallyconnectedtothenon-invertinginputofthePWM

comparator.Anoptimalfiltercombinationischosenandconnectedtothispinandeither

ground or VFB to stabilize the voltage mode loop.

Enable Pin. Pulling this pin below 0.4V will place the IC into sleep mode. This pin is internally

pulled to VCC with a µA current source.

PWRGD Power Good Output. This open drain output is pulled low when VOUT is outside of the

regulation. Connect an external resistor to pull high.

Soft Start/Fault Flag. Connect an external capacitor between SS and GND to set the soft start

rate based on the 0µA source current. The SS pin is held low via a mA (min) current during

all fault conditions.

ISN

Negative Input for the Sense Comparator. There should be a 60mV offset between PSENSE

and NSENSE. Offset accuracy +0%.

ISP

Positive Input for the Inductor Current Sense.

SWN Lower supply rail for the GH high-side gate driver. Connect this pin to the switching node at

the junction between the two external power MOSFET transistors.

High current driver output for the high side NFET switch. It is always low if GL is high or during a fault.

BST High side driver supply pin. Connect BST to the external boost diode and capacitor as shown

in the Application Schematic of page . High side driver is connected between BST pin and SWN pin.

VIN

Supply Input -- supplies power to the internal LDO.

UVIN Under Voltage lock-out for VIN voltage. Internally has a resistor divider from VIN to ground.

Can be overridden with external resistors.

VCC Output of the Internal LDO. If VIN is less than 5V then Vcc should be powered from an

external 5V supply.

Note: Die attach paddle is internally connected to GND.

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