WM8581 datasheet(50/100 Pages) WOLFSON

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WM8581

Production Data

PD Rev 4.0 April 2007

OSCILLATOR

The function of the oscillator is to generate the OSCCLK oscillator clock signal. This signal may be

used as:

•

The clock source for the PLLs.

•

A selectable clock source for the MCLK pin, when the pin is configured as an output.

•

A selectable clock source for the CLKOUT pin, when enabled.

Whenever the PLLs or the S/PDIF receiver is enabled, the OSCCLK signal must be present to

enable the PLLs to generate the necessary clock signals.

The oscillator uses a Pierce type oscillator drive circuit. This circuit requires an external crystal and

appropriate external loading capacitors. The oscillator circuit contains a bias generator within the

WM8581 and hence an external bias resistor is not required. Crystal frequencies between 10 and

14.4MHz or 16.28MHz and 27MHz can be used in software mode. In this case the oscillator XOUT

must be powered up using the OSCPD bit. The recommended circuit is shown in the recommended

components diagram, please refer to Figure 49.

Alternatively, an external CMOS compatible clock signal can be applied to the XIN pin in the absence

of a crystal. This is not recommended when using the PLL as the PLL requires a jitter-free OSCCLK

signal for optimum performance. In this case the oscillator XOUT can be powered down using the

OSCPD bit.

The oscillator XOUT pin has one control bit as shown in Table 39.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R51

PWRDN 2

33h

OSCPD

Oscillator XOUT Power Down

0 = Power Up XOUT (crystal mode)

1 = Power Down XOUT (CMOS

clock input mode)

Table 39 Oscillator Control

PHASE-LOCKED LOOP (PLL)

The WM8581 has two on-chip phase-locked loop (PLL) circuits which can be used to synthesise two

independent clock signals (PLLACLK and PLLBCLK) from the external oscillator clock. The PLLs can

be used to:

•

Generate clocks necessary for the S/PDIF receiver to lock on to and recover S/PDIF data from an

incoming S/PDIF data stream.

•

Generate clocks which may be used to drive the MCLK and/or CLKOUT pins.

•

Generate clocks which may be used by the S/PDIF transmitter to encode and transmit a S/PDIF

data stream.

•

Generate clocks which may be used as the master clock source for the the ADC and DACs.

•

Generate clocks which may be used by the master mode clock generator to generate the BCLK

and LRCLK signals for the digital audio interfaces.

The PLLs can be enabled or disabled using the register bits shown in Table 40.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

PLLAPD

R51

PWRDN 2

33h

PLLBPD

PLL Power Down Control

0 = Power Up PLL

1 = Power Down PLL

Table 40 PLL Power Down Control

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