WM8580 datasheet(51/92 Pages) WOLFSON

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WM8580

PD Rev 4.0 February 2007

S/PDIF RECEIVE MODE CLOCKING

In S/PDIF receive mode, the PLLA_N and PLLA_K values are automatically controlled by the

S/PDIF receiver to allow the receiver to use PLLA to lock on to and track the incoming S/PDIF data

stream. PLLB must be configured to produce a specific reference clock frequency for the S/PDIF

receiver.

The S/PDIF receiver has four clocking modes based on the incoming S/PDIF stream sample rate.

The modes are:

•

Mode 1: Incoming S/PDIF Sample Rate = 192kHz +/- 1%

•

Mode 2: Incoming S/PDIF Sample Rate = 88.2kHz -1% to 96kHz +1%

•

Mode 3: Incoming S/PDIF Sample Rate = 44.1kHz -1% to 48kHz +1%

•

Mode 4: Incoming S/PDIF Sample Rate = 32kHz +/- 1%

Before the S/PDIF receiver is enabled, it is important that the PLLB_N and PLLB_K register values

(and the PRESCALE_x values as appropriate) are manually configured in a specific default state.

The PLLB_N and PLLB_K register values (and the PRESCALE_x values as appropriate) must also

be manually re-configured when a change of the clocking mode is detected and the change is to

mode 1 or from mode 1. Note that the PRESCALE_A value must always be set to the same value as

PRESCALE_B.

The specified PLLB f2 frequencies that must be configured using the PLLB_N and PLLB_K register

values (and the PRESCALE_x values as appropriate) for reception of specific S/PDIF sample rates

are as follows:

•

Mode 1 (192kHz Sample Rate): PLLB f2 = 98.304MHz

•

Modes 2/3/4 (32/44.1/48/88.2/96kHz Sample Rates): PLLB f2 = 94.3104MHz

The FREQMODE_B[1:0] bits and POSTSCALE_B bit are not used in PLL S/PDIF recever mode.

The PLL register settings are configured by default to allow 32/44.1/48/88.2/96kHz (modes 2/3/4)

sample rate S/PDIF receiver operation using a 12MHz crystal clock. The appropriate PLLB register

values must be updated if:

•

Any crystal clock frequency other than 12MHz is used.

•

A S/PDIF stream with 192kHz sample rate (mode 1) is detected.

In either case, reprogramming of the PLLB_N and PLLB_K values (and the PRESCALE_x values as

appropriate) is necessary.

Refer to Table 47 for details of a number of recommended PLLB configurations. Many other

configurations are possible; please refer to PLL Configuration section for details regarding how to

calculate alternative settings.

WM8580 Datasheet(PDF) 51 Page - Wolfson Microelectronics plc

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