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WM8980 Datasheet(PDF) 97 Page - Wolfson Microelectronics plc |
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WM8980 Datasheet(HTML) 97 Page - Wolfson Microelectronics plc |
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97 / 112 page ![]() Pre-Production WM8980 w PP Rev 3.1 March 2007 97 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 39 (27h) 8:0 PLLK[8:0] 011101001 Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Master Clock and Phase Locked Loop (PLL) 8:2 000000 Reserved 4 QBOOST 0 Increases ‘Q’ of video filter Video Buffer 1 VBGAIN 0 Video buffer gain 0 = 0dB (=6dB unloaded) 1 = +6dB (=12dB unloaded) Video Buffer 40 (28h) 0 VBCLAMPEN 0 Video buffer clamp enable 0 = disabled 1 = enabled Video Buffer 8:4 00000 Reserved 41 (29h) 3:0 DEPTH3D 0000 Stereo depth 0000: 0% (minimum 3D effect) 0001: 6.67% .... 1110: 93.3% 1111: 100% (maximum 3D effect) 3D Stereo Enhancement 8:6 000 Reserved 5 MUTERPGA 2INV 0 Mute input to INVROUT2 mixer Analogue Outputs 4 INVROUT2 0 Invert ROUT2 Output Analogue Outputs 3:1 BEEPVOL 000 AUXR input to ROUT2 inverter gain 000 = -15dB ... 111 = +6dB Analogue Outputs 43 (2Bh) 0 BEEPEN 0 0 = mute AUXR beep input 1 = enable AUXR beep input Analogue Outputs 8 MBVSEL 0 Microphone Bias Voltage Control 0 = 0.9 * AVDD 1 = 0.6 * AVDD Input Signal Path 7 0 Reserved 6 R2_2INP PGA 0 Connect R2 pin to right channel input PGA positive terminal. 0=R2 not connected to input PGA 1=R2 connected to input PGA amplifier positive terminal (constant input impedance). Input Signal Path 5 RIN2INP PGA 1 Connect RIN pin to right channel input PGA negative terminal. 0=RIN not connected to input PGA 1=RIN connected to right channel input PGA amplifier negative terminal. Input Signal Path 4 RIP2INP PGA 1 Connect RIP pin to right channel input PGA amplifier positive terminal. 0 = RIP not connected to input PGA 1 = right channel input PGA amplifier positive terminal connected to RIP (constant input impedance) Input Signal Path 44 (2Ch) 3 0 Reserved |
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