AD1870

REV. A

–16–

BCLK

RDEDGE = LO

BCLK

RDEDGE = HI

31

32

1

2

3

16

SOUT

OUTPUT

WCLK

OUTPUT

TAG

OUTPUT

LSB

LEFT TAG

LSB

RIGHT TAG

31

32

1

2

3

16

MSB-1

LEFT DATA

MSB-2

LSB

MSB-1

RIGHT DATA

MSB-2

LSB

ZEROS

ZEROS

ZEROS

L

RCK

OUTPUT

OUTPUT

17

18

17

18

MSB

MSB

MSB

MSB

Figure 13. Serial Data Output Timing: Master Mode, Left-Justified with No MSB Delay,

S/

M = LO, RLJUST = LO, MSBDLY = Hl

BCLK

RDEDGE = LO

BCLK

RDEDGE = HI

32

12

34

17

SOUT

OUTPUT

WCLK

OUTPUT

TAG

OUTPUT

MSB

LEFT TAG

MSB

RIGHT TAG

31

32

1

2

3

4

17

MSB-1

LEFT DATA

MSB-2

LSB

MSB-1

RIGHT DATA

MSB-2

LSB

ZEROS

ZEROS

ZEROS

OUTPUT

L

RCK

OUTPUT

MSB

LSB

MSB

LSB

M = LO, RLJUST = LO,

MSBDLY = LO

BCLK

RDEDGE = LO

BCLK

RDEDGE = HI

31

32

1

2

3

4

16

SOUT

OUTPUT

WCLK

OUTPUT

TAG

OUTPUT

19

20

21

32

1

2

INPUT

HI

HI

517

18

LSB

LEFT TAG

MSB

LSB

RIGHT TAG

LEFT TAG

LSB

MSB-14

LSB

PREVIOUS DATA

MSB-1 MSB-2 MSB-3

LEFT DATA

MSB-4

MSB-3 MSB-4

LSB

MSB-1 MSB-2

RIGHT DATA

LSB

MSB-1

LEFT DATA

L

RCK

INPUT

MSB

MSB

MSB

MSB

MSB

Figure 15. Serial Data Output Timing: Slave Mode, Left-Justified with No MSB Delay,

32-Bit Frame Mode, S/

M = Hl, RLJUST = LO, MSBDLY = Hl