AD1870 datasheet(17/20 Pages) AD

17 / 20 page

AD1870

REV. A

–17–

BCLK

RDEDGE = LO

BCLK

RDEDGE = HI

SOUT

OUTPUT

TAG

OUTPUT

INPUT

WCLK

OUTPUT

618

MSB

LEFT TAG

MSB

LSB

RIGHT TAG

MSB-14

LSB

PREVIOUS DATA

MSB-1 MSB-2 MSB-3

LEFT DATA

MSB-4

MSB-3 MSB-4

LSB

MSB-1 MSB-2

RIGHT DATA

LSB

MSB-1

LEFT DATA

MSB

LEFT TAG

MSB

RIGHT TAG

RCK

INPUT

MSB

LSB

MSB

LSB

Figure 16. Serial Data Output Timing: Slave Mode, I 2S-Justified, 32-Bit Frame Mode,

M = Hl, RLJUST = LO, MSBDLY = LO

BCLK OUTPUT (64 x

fS)

RDEDGE = LO

CLKIN

INPUT

BCLK OUTPUT (64 x

fS)

RDEDGE = HI

WCLK

OUTPUT

DATA AND TAG

OUTPUTS

tDLYCKB

tBPWL

tBPWH

tBPWL

tBPWH

tDLYBLR

tDLYDT

tDLYBWR

tDLYBWF

RCK

OUTPUT

XMIT

Figure 17. Master Mode Clock Timing

WCLK

INPUT

DATA AND TAG

OUTPUTS

XMIT

tBPWL

tBPWH

tBPWL

tDLYLRDT

MSB

MSB-1

tDLYBDT

tSETLRBS

BCLK INPUT

RDEDGE = LO

BCLK OUTPUT

RDEDGE = HI

RCK

INPUT

tSETWBS

SAMPLE

XMIT

SAMPLE

Figure 18. Slave Mode Clock Timing

CLKIN INPUT

RESET INPUT

tCPWH

tCPWL

tCLKIN

tRPWL

Figure 19. CLKIN and

RESET Timing

AD1870 Datasheet(PDF) 17 Page - Analog Devices

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