AD8315ARM datasheet(14/24 Pages) AD

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AD8315

Rev. C | Page 14 of 24

First, the summed detector currents are written as a function of

the input

IDET

= ISLP log10 (VIN/VZ)

(3)

where:

IDET

is the partially filtered demodulated signal, whose

exact average value is extracted through the subsequent

integration step.

ISLP

is the current-mode slope and has a value of 115 μA per

decade (that is, 5.75 μA/dB).

VIN

is the input in V rms.

is the effective intercept voltage, which, as previously noted,

is dependent on waveform but is 316 μV rms (−70 dBV) for a

sine wave input.

Now the current generated by the setpoint interface is simply

ISET(4)

= VSET/415 kΩ

(4)

The difference between this current and IDET is applied to the

loop filter capacitor CFLT. It follows that the voltage appearing

on this capacitor, VFLT, is the time integral of the difference

current:

VFLT(s)

= (ISET − IDET)/sCFLT

(5)

(

)

FLT

SLP

SET

log

kΩ

4.15

−

(6)

The control output VAPC is slightly greater than this, because the

gain of the output buffer is ×1.35. In addition, an offset voltage

is deliberately introduced in this stage; this is inconsequential

because the integration function implicitly allows for an

arbitrary constant to be added to the form of Equation 6. The

polarity is such that VAPC rises to its maximum value for any

value of VSET greater than the equivalent value of VIN. In

practice, the VAPC output rails to the positive supply under this

condition unless the control loop through the power amplifier

is present. In other words, the AD8315 seeks to drive the RF

power to its maximum value whenever it falls below the

setpoint. The use of exact integration results in a final error that

is theoretically 0, and the logarithmic detection law would

ideally result in a constant response time following a step

change of either the setpoint or the power level, if the power-

amplifier control function were likewise linear in dB. However,

this latter condition is rarely true, and it follows that in practice,

the loop response time depends on the power level, and this

effect can strongly influence the design of the control loop.

Equation 6 can be restated as

()

(

)

SLP

SET

APC

log

−

(7)

where VSLP is the volts-per-decade slope from Equation 1,

having a value of 480 mV/decade, and T is an effective time

constant for the integration, being equal to 4.15 kΩ × CFLT/1.35;

the resistor value comes from the setpoint interface scaling

Equation 4 and the factor 1.35 arises because of the voltage gain

of the buffer. Therefore, the integration time constant can be

written as

= 3.07 CFLT in μs, when C is expressed in nF

(8)

To simplify our understanding of the control loop dynamics,

begin by assuming that the power amplifier gain function is

actually linear in dB, and for the moment, use voltages to

express the signals at the power amplifier input and output.

Let the RF output voltage be VPA and let its input be VCW.

Furthermore, to characterize the gain control function, this

form is used

(

)

GBC

APC V

(9)

where:

is the gain of the power amplifier when VAPC = 0.

VGBC

is the gain scaling.

While few amplifiers conform so conveniently to this law, it

provides a clearer starting point for understanding the more

complex situation that arises when the gain control law is less ideal.

This idealized control loop is shown in Figure 34. With some

manipulation, it is found that the characteristic equation of this

system is

() (

)

(

)

GBC

SLP

GBC

SET

APC

−

log

(10)

where:

is the coupling factor from the output of the power amplifier

to the input of the AD8315 (for example, ×0.1 for a 20 dB coupler).

is a modified time constant (VGBC/VSLP)T.

This is quite easy to interpret. First, it shows that a system of

this sort exhibits a simple single-pole response, for any power

level, with the customary exponential time domain form for

either increasing or decreasing step polarities in the demand

level VSET or the carrier input VCW. Second, it reveals that the

final value of the control voltage VAPC is determined by several

fixed factors:

(

) (

)

(

)

SLP

GBC

SET

APC

log

−

∞

(11)

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