AD8324

Rev. A | Page 6 of 16

PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS

TOP VIEW

(Not to Scale)

AD8324

1

2

3

4

5

15

14

13

12

11

16

17

20 19 18

67

8

9

10

GND

GND

GND

RAMP

BYP

NC

TOP VIEW

(Not to Scale)

20

19

18

17

16

15

14

13

12

11

1

2

3

4

5

6

7

8

9

10

AD8324

TXEN

SDATA

CLK

SLEEP

BYP

NC

NC = NO CONNECT

GND

GND

GND

GND

GND

RAMP

GND

DATEN

Figure 5. 20-Lead LFCSP

Figure 6. 20-Lead QSOP

Table 6. Pin Function Descriptions

Pin No.

Pin No.

20-Lead

LFCSP

20-Lead

QSOP

Mnemonic

Description

1, 2, 5, 9,

18, 19

1, 3, 4, 7,

11, 20

GND

Common External Ground Reference.

17, 20

2, 19

Common Positive External Supply Voltage.

3

5

capacitor.

4

6

6

8

DATEN

Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A

Logic 0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and

simultaneously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data

latch (holds the previous and simultaneously enables the register for serial data load).

7

9

SDATA

Serial Data Input. This digital input allows an 8-bit serial (gain) word to be loaded into the internal

register with the MSB (most significant bit) first.

8

10

CLK

Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-

slave shift register. Logic 0-to-1 transition latches the data bit, and a 1-to-0 transfers the data bit

to the slave. This requires the input serial data-word to be valid at or before this clock transition.

10

12

SLEEP

Low Power Sleep Mode. In the sleep mode, the AD8324’s supply current is reduced to 30 μA. A

12

14

BYP

Internal Bypass. This pin must be externally decoupled (0.1 μF capacitor).

13

15

14

16

15

17

RAMP

External RAMP Capacitor (Optional).

16

18

TXEN

Logic 0 disables forward transmission. Logic 1 enables forward transmission.