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IOCP

tRETRY

tOCP

Overshoot due to OCP

deglitch time (tOCP)

Motor

Current

Time

Figure 9-6. OCP Operation

Overcurrent conditions are detected independently on both high- and low-side FETs. This means that a short

to ground, supply, or across the motor winding will all result in an overcurrent shutdown. Overcurrent protection

does not use the current sense circuitry used for current regulation, so it functions regardless of VREF and

IPROPI settings.

9.4.3.2 Thermal Shutdown (TSD)

If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin asserts

low. Once the die temperature has fallen to a safe level, operation will automatically resume.

Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient

heatsinking, or an ambient temperature outside of the Recommended Operating Conditions.

9.4.3.3 Undervoltage Lockout (UVLO)

Whenever the voltage on the VM pin falls below the UVLO falling threshold voltage, VUVLO, all circuitry in the

device is disabled, the output FETS are disabled, and all internal logic is reset. Normal operation resumes when

the VVM voltage rises above the UVLO rising threshold as shown in Figure 9-7. The nFAULT pin is driven low

during an undervoltage condition and is released after operation starts again.

When VVM is close to 0 V, the internal circuitry may not bias properly, and the open-drain pull-down on the

nFAULT pin may release.

VUVLO (min) falling

VUVLO (max) falling

VUVLO (max) rising

VUVLO (min) rising

VVM

nFAULT

DEVICE ON

DEVICE OFF

DEVICE ON

Time

Figure 9-7. VM UVLO Operation

9.5 Device Functional Modes

Table 9-4 summarizes the DRV8411A functional modes described in this section.

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DRV8411A

SLVSGI9A – OCTOBER 2022 – REVISED JULY 2023

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