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AT83C5103 Datasheet(PDF) 46 Page - ATMEL Corporation |
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AT83C5103 Datasheet(HTML) 46 Page - ATMEL Corporation |
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46 / 64 page ![]() 46 AT8xC5103 4134C–8051–09/04 Interrupt System The AT8xC5103 has a total of 5 interrupt vectors: one external interrupt INT0, two timer interrupts (timers 0, 1), PCA and SPI. These interrupts are shown in Figure 27.. Figure 27. Interrupt Control System Each of the interrupt sources can be individually enabled or disabled by setting or clear- ing a bit in the Interrupt Enable register (see Table 31). This register also contains a global disable bit, which must be cleared to disable all interrupts at once. Each interrupt source can also be individually programmed to one of four priority levels by setting or clearing a bit in the Interrupt Priority register (see Table 33) and in the Inter- rupt Priority High register (see Table 35). Table 30 shows the bit values and priority levels associated with each combination. IE1 0 3 High Priority Interrupt Interrupt Polling Sequence Low Priority Interrupt Global Disable Individual Enable NC NC TF0 INT0 INT1 TF1 IPH, IP IE0 0 3 0 3 0 3 0 3 0 3 NC SPI 0 3 NC 0 3 0 3 CF CCFx PCA NC |
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