M68HC05 datasheet(49/302 Pages) FREESCALE

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MC68HC05B6

Rev. 4.1

Freescale

3-7

MEMORY AND REGISTERS

EE1P – EEPROM protect bit

In order to achieve a higher degree of protection, the EEPROM is effectively split into two parts,

both working from the VPP1 charge pump. Part 1 of the EEPROM array (32 bytes from $0100 to

$011F) cannot be protected; part 2 (224 bytes from $0120 to $01FF) is protected by the EE1P bit

of the options register.

1 (set)

–

Part 2 of the EEPROM array is not protected; all 256 bytes of EEPROM

can be accessed for any read, erase or programming operations

0 (clear) –

Part 2 of the EEPROM array is protected; any attempt to erase or

program a location will be unsuccessful

When this bit is set to 1 (erased), the protection will remain until the next power-on or external

reset. EE1P can only be written to ‘0’ when the ELAT bit in the EEPROM control register is set.

SEC – Security bit

This high security bit allows the user to secure the EEPROM data from external accesses. When

the SEC bit is at ‘0’, the EEPROM contents are secured by preventing any entry to test mode. The

only way to erase the SEC bit to ‘1’ externally is to enter self-check mode, at which time the entire

EEPROM contents will be erased. When the SEC bit is changed, its new value will have no effect

until the next external or power-on reset.

3.6

EEPROM during STOP mode

When entering STOP mode, the EEPROM is automatically set to the read mode and the VPP1

high voltage charge pump generator is automatically disabled.

3.7

EEPROM during WAIT mode

The EEPROM is not affected by WAIT mode. Any program/erase operation will continue as in

normal operating mode. The charge pump is not affected by WAIT mode, therefore it is possible

to wait the tERA1 erase time or tPROG1 programming time in WAIT mode.

Under normal operating conditions, the charge pump generator is driven by the internal CPU

clocks. When the operating frequency is low, e.g. during WAIT mode, the clocking should be done

by the internal A/D RC oscillator. The RC oscillator is enabled by setting the ADRC bit of the A/D

status/control register at $0009.

M68HC05 Datasheet(PDF) 49 Page - Freescale Semiconductor, Inc